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부품번호 | NBSG111 기능 |
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기능 | 2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver | ||
제조업체 | ON Semiconductor | ||
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NBSG111
2.5V/3.3V SiGe Differential
1:10 Clock/Data Driver
with RSECL* Outputs
*Reduced Swing ECL
Description
The NBSG111 is a 1−to−10 differential clock/data driver. The
device is functionally equivalent to the LVEP111 device with much
higher bandwidth and lower EMI capabilities.
Inputs incorporate internal 50 W termination resistors (input to VT
pad) and accept NECL (Negative ECL), PECL (Positive ECL),
LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced
Swing ECL), 400 mV.
The Q[0:9] / Q[0:9] outputs have a differential synchronous enable
(EN/EN) pin. The synchronous enable pin is used to avoid a runt clock
pulse when the device is enabled/disabled as can happen with an
asynchronous control. The internal flip flop is clocked on the falling
edge of selected clock (CLK0/CLK0 or CLK1/CLK1), therefore all
associated specification limits are referenced to the negative edge of
the selected clock input.
The VBB and VMM pins are internally generated voltage supplies
available
or PECL
to this
inputs
device only. The VBB
and the VMM pin is
is used for single−ended NECL
used for LVCMOwwSw.DiantapSuhetest4.U.Fcomor
single−ended input operation, the unused differential input is
connected to VBB or VMM as a switching reference voltage. VBB or
VMM may also rebias AC coupled inputs. When used, decouple VBB
and VMM via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB and VMM outputs should be left open.
Features
• Maximum Input Clock Frequency > 6 GHz Typical
• Maximum Input Data Rate > 6 Gb/s Typical
• 300 ps Typical Propagation Delay
• 60 ps Typical Rise and Fall Times
• RSPECL Output with Operating Range: VCC = 2.375 V to
3.465 V with VEE = 0 V
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
• RSECL Output Level (400 mV Peak−to−Peak Output), Differential
Output
• 50 W Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP and EP Devices
• VBB and VMM Reference Voltage Output
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MARKING
DIAGRAM*
SG
111
LYW
FCBGA−49
BA SUFFIX
CASE 489A
SG111
L
Y
W
= Device Code
= Wafer Lot
= Year
= Work Week
*For further details, refer to Application Note
AND8002/D
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 8
1
Publication Order Number:
NBSG111/D
NBSG111
Table 2. FUNCTION TABLE
SEL EN
LL
LH
HL
HH
Active Input
Disabled Outputs
CLK0, CLK0
Disabled Outputs
CLK1, CLK1
2. SEL/EN are the inverse of SEL/EN unless specified otherwise.
(C5) VTSEL
(C6) SEL
RTIN
R1
R2
(E4) VTCLK0
(F4) CLK0
(F5) CLK0
(E5) VTCLK0
(B4) CLK1
(C4) VTCLK1
(B3) CLK1
(C3) VTCLK1
(D6) SEL
(D5) VTSEL
RTIN
R2
RTIN
R1
R2
RTIN R2 R1
RTIN
R2
RTIN R2
(D3) VTEN
(D2) EN
RTIN
0 R2
SYNC
1 R1
(E2) EN
(E3) VTEN
RTIN
R2
(F6) VBB
(A1, A7, G1, G7) VEE
(B5, D4, F3) VCC
(B2) VMM
Figure 2. Logic Diagram
Q0 (B1)
Q0 (C1)
Q1 (D1)
Q1 (E1)
Q2 (F1)
Q2 (G2)
Q3 (G3)
Q3 (G4)
Q4 (G5)
Q4 (G6)
Q5 (F7)
Q5 (E7)
Q6 (D7)
Q6 (C7)
Q7 (B7)
Q7 (A6)
Q8 (A5)
Q8 (A4)
Q9 (A3)
Q9 (A2)
Table 3. INTERFACING OPTIONS
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
CONNECTIONS
Connect VTCLK0, VTCLK1, VTEN, VTSEL and
VTCLK0, VTCLK1, VTEN, VTSEL to VCC
Connect VTCLK0, VTCLK1, VTEN, VTSEL and
VTCLK0, VTCLK1, VTEN, VTSEL Together
Bias VTCLK0, VTCLK1, VTEN, VTSEL and
VTCLK0, VTCLK1, VTEN, VTSEL Inputs within
Common Mode Range (VIHCMR)
Standard ECL Termination Techniques
See Text on Page 1. Unused Differential Input Switching Voltage
Reference Range is from VEE + 1125 mV to VCC − 75 mV
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4페이지 NBSG111
Table 7. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 11)
−40°C
25°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min
IEE Negative Power Supply Current
70 85 110 70 85 110 70
VOH Output HIGH Voltage (Note 6)
2165 2320 2415 2210 2330 2460 2235
VOUTPP Output Voltage Amplitude
305 420 545 305 420 545 305
VIH Input HIGH Voltage
(Single−Ended) (Notes 8 and 9)
VTHR VCC − VCC VTHR VCC − VCC VTHR
+ 75 1000*
+ 75 1000*
+ 75
70°C
Typ
85
2360
420
VCC −
1000*
Max
110
2485
545
VCC
Unit
mA
mV
mV
mV
VIL Input LOW Voltage
(Single−Ended) (Notes 8 and 10)
VIH − VCC − VTHR VIH − VCC − VTHR VIH − VCC − VTHR mV
2500 1400* − 75 2500 1400* − 75 2500 1400* − 75
VBB
VIHCMR
PECL Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 7)
1825
1.2
1900
2065
3.3
1825
1.2
1900
2065
3.3
1825
1.2
1900
2065
3.3
mV
V
VMM
RTIN
IIH
IIL
LVCMOS Output Voltage Reference
(@ 3.3 VCC)
Internal Input Termination Resistor
Input HIGH Current (@ VIH)
Input LOW Current (@ VIL)
1450
45
1650
50
30
25
1850
55
100
100
1450
45
1650
50
30
25
1850
55
100
100
1450
45
1650
50
30
25
1850
55
100
100
mV
W
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V. VMM varies (VCC − VEE) / 2 with VCC and VEE.
6. All outputs loaded with 50 W to VCC − 1.5 V. VOH/VOL measured at VIH/VIL (Typical).
7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
8. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR − 75 mV.
9. VIH cannot exceed VCC.
10. VIL always w VEE.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V. VMM varies (VCC − VEE) / 2 with VCC and VEE.
*Typicals used for testing purposes.
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부품번호 | 상세설명 및 기능 | 제조사 |
NBSG11 | 2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs | ON |
NBSG111 | 2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |