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PDF NBSG72A Data sheet ( Hoja de datos )
| Número de pieza | NBSG72A | |
| Descripción | 2.5V/3.3V SiGe Differential 2 x 2 Crosspoint Switch | |
| Fabricantes | ON Semiconductor | |
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NBSG72A
2.5V/3.3V SiGe Differential
2 x 2 Crosspoint Switch
with Output Level Select
The NBSG72A is a high−bandwidth fully differential 2 X 2
crosspoint switch with Output Level Select (OLS) capabilities. This is
a part of the GigaComm™ family of high performance Silicon
Germanium products. The device is housed in a low profile 3 X 3 mm
16−pin QFN package.
Differential inputs incorporate internal 50 W termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to
program the peak−to−peak output amplitude between 0 mV and
800 mV in five discrete steps. The SELECT inputs are single−ended
and can be driven with either LVECL or LVCMOS/LVTTL
input levels.
Features
• Maximum Input Clock Frequency > 7 GHz Typical
• Maximum Input Data Rate > 7 Gb/s Typical
• 200 ps Typical Propagation Delay (OLS = FLOAT)
• 55/45 ps Typical Rise/Fall Times (OLS = FLOAT)
• Selectable Swing PECL Output with Operating Range:www.DataSheet4U.com
VCC = 2.375 V to 3.465 V with VEE = 0 V
• Selectable Swing NECL Output with NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
• Selectable Output Levels (0 mV, 200 mV, 400 mV, 600 mV or
800 mV Peak−to−Peak Output)
• 50 W Internal Input Termination Resistors
• Single−Ended LVECL or LVCMOS/LVTTL Select Inputs
(SELA, SELB)
• Pb−Free Packages are Available
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
ÇÇÇÇ16
1
SG
72A
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
1
Publication Order Number:
NBSG72A/D
1 page  
NBSG72A
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 3)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE
VOH
VOL
VOUTPP
VIH
Negative Power Supply Current
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
Output Voltage Amplitude
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
Input HIGH Voltage (Single−Ended)
(Note 6)
D0, D0, D1, D1
40
1460
555
1235
775
1455
1005
670
125
510
0
325
VEE +
1275
55
1510
705
1295
895
1505
1095
800
215
615
5
415
VCC −
1000*
65
1560
855
1385
1015
1585
1215
VCC
40
1490
55
1540
595
1270
810
1490
1040
745
1330
930
1540
1130
660 795
120 210
505 610
00
320 410
VEE + VCC −
1275 1000*
65
1590
895
1420
1050
1620
1250
VCC
40
1515
55
1565
625
1295
840
1510
1065
775
1355
960
1560
1155
655
120
500
0
320
VEE +
1275
790
210
605
5
410
VCC−
1000*
65
1615
925
1445
1080
1640
1275
VCC
mA
mV
mV
mV
mV
VIL Input LOW Voltage (Single−Ended)
VEE VCC− VIH− VEE VCC− VIH− VEE VCC− VIH− mV
(Note 7)
D0, D0, D1, D1
1400* 150
1400* 150
1400* 150
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 5)
1.2
2.5 1.2
2.5 1.2
2.5 V
RTIN
Internal Input Termination Resistor
45 50 55 45 50 55 45 50 55 W
IIH Input HIGH Current (@VIH)
35 100
35 100
35 100 mA
IIL Input LOW Current (@VIL)
20 100
20 100
20 100 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V.
4. All loading with 50 W to VCC − 2.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
6. VIH cannot exceed VCC.
7. VIL always w VEE.
http://onsemi.com
5
5 Page 
NBSG72A
Total System Jitter = 17.2 ps
Input Generator Jitter = 10 ps
Device Jitter = 6.8 ps
X = 60 ps/div
Figure 8. Eye Diagram at 3.2 Gb/s
(VCC − VEE = 3.3 V, OLS = FLOAT @ 255C with input pattern of 231−1 PRBS, 5000 Waveforms)
Total System Jitter = 17.2 ps
Input Generator Jitter = 10 ps
Device Jitter = 7.2 ps
X = 21 ps/div
Figure 9. Eye Diagram at 7 Gb/s/s
(VCC − VEE = 3.3 V, OLS = FLOAT @ 255C with input pattern of 231−1 PRBS, 5000 Waveforms)
300
200
100
0
−100
−200
−300
−400
−500
−600
−700
VCC
VCC − 400
VCC − 800
VCC − 1200
VEE
VOLS (mV)
Figure 10. Typical OLS Input Current vs. OLS Input Voltage
(VCC − VEE = 3.3 V @ 255C)
http://onsemi.com
11
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