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PDF AT45D021A Data sheet ( Hoja de datos )
| Número de pieza | AT45D021A | |
| Descripción | 2-megabit 5-volt Only Serial DataFlash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 100% Compatible to AT45D021
• Single 4.5V - 5.5V Supply
• Serial Interface Architecture
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 1024 Pages (264 Bytes/Page) Main Memory
• Optional Page and Block Erase Operations
• Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
• Continuous Read Capability through Entire Array
• Internal Program and Control Timer
• Low Power Dissipation
– 15 mA Active Read Current Typical
– 10 µA CMOS Standby Current Typical
• 15 MHz Max Clock Frequency
• Hardware Data Protection Feature
• Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Description
The AT45D021A is a 5-volt only, serial interface Flash memory suitable for in-system
reprogramming. Its 2,162,688 bits of memory are organized as 1024 pages of
264 bytes each. In addition to the main memory, the AT45D021A also contains two
SRAM data buffers of 264 bytes each. The buffers allow receiving of data while a
page in the main memory is being reprogrammed. Unlike conventional Flash
Pin Configurations
www.DataSheet4U.com
(continued)
Pin Name
CS
SCK
SI
SO
WP
RESET
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write
Protect Pin
Chip Reset
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TSOP Top View
Type 1
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
RDY/BUSY Ready/Busy
PLCC
SOIC
SCK
SI
SO
NC
NC
NC
NC
NC
NC
5
6
7
8
9
10
11
12
13
29 WP
28 RESET
27 RDY/BUSY
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
Note: PLCC package pins 16
and 17 are DON’T CONNECT.
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 NC
26 NC
25 WP
24 RESET
23 RDY/BUSY
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
2-megabit
5-volt Only
Serial
DataFlash®
AT45D021A
Recommend using
AT45DB021B for new
designs.
Rev. 1639C–01/01
1
1 page  
AT45D021A
Status Register Format
Bit 7
RDY/BUSY
Bit 6
COMP
Bit 5
0
Bit 4
1
Bit 3
0
Bit 2
X
Bit 1
X
Bit 0
X
Ready/Busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can
cause the device to be in a busy state: Main Memory Page
to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program with Built-in Erase,
Buffer to Main Memory Page Program without Built-in
Erase, Page Erase, Block Erase, Main Memory Page Pro-
gram, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer
Compare operation is indicated using bit 6 of the status
register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at
least one bit of the data in the main memory page does not
match the data in the buffer.
The device density is indicated using bits 5, 4, and 3 of the
status register. For the AT45D021A, the three bits are 0, 1,
and 0. The decimal value of these three binary bits does
not equate to the device density; the three bits represent a
combinational code relating to differing densities of Serial
DataFlash devices, allowing a total of eight different density
configurations.
Program and Erase Commands
BUFFER WRITE: Data can be shifted in from the SI pin
into either buffer 1 or buffer 2. To load data into either
buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,
must be followed by 15 don’t care bits and nine address
bits (BFA8-BFA0). The nine address bits specify the first
byte in the buffer to be written. The data is entered follow-
ing the address bits. If the end of the data buffer is reached,
the device will wrap around back to the beginning of the
buffer. Data will continue to be loaded into the buffer until a
low-to-high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE: Data written into either buffer 1 or buffer
2 can be programmed into the main memory. To start the
operation, an 8-bit opcode, 83H for buffer 1 or 86H for
buffer 2, must be followed by the five reserved bits, 10
address bits (PA9-PA0) that specify the page in the main
memory to be written, and nine additional don’t care bits.
When a low-to-high transition occurs on the CS pin, the
part will first erase the selected page in main memory to all
1s and then program the data stored in the buffer into the
specified page in the main memory. Both the erase and the
programming of the page are internally self-timed and
should take place in a maximum time of tEP. During this
time, the status register will indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-
OUT BUILT-IN ERASE: A previously erased page within
main memory can be programmed with the contents of
either buffer 1 or buffer 2. To start the operation, an 8-bit
opcode, 88H for buffer 1 or 89H for buffer 2, must be
followed by the five reserved bits, 10 address bits (PA9-
PA0) that specify the page in the main memory to be writ-
ten, and nine additional don’t care bits. When a low-to-high
transition occurs on the CS pin, the part will program the
data stored in the buffer into the specified page in the main
memory. It is necessary that the page in main memory that
is being programmed has been previously erased. The pro-
gramming of the page is internally self-timed and should
take place in a maximum time of tP. During this time, the
status register will indicate that the part is busy.
PAGE ERASE: The optional Page Erase command can be
used to individually erase any page in the main memory
array allowing the Buffer to Main Memory Page Program
without Built-in Erase command to be utilized at a later
time. To perform a Page Erase, an opcode of 81H must be
loaded into the device, followed by five reserved bits,
10 address bits (PA9-PA0), and nine don’t care bits. The
nine address bits are used to specify which page of the
memory array is to be erased. When a low-to-high transi-
tion occurs on the CS pin, the part will erase the selected
page to 1s. The erase operation is internally self-timed and
should take place in a maximum time of tPE. During this
time, the status register will indicate that the part is busy.
BLOCK ERASE: A block of eight pages can be erased at
one time allowing the Buffer to Main Memory Page Pro-
gram without Built-in Erase command to be utilized to
reduce programming times when writing large amounts of
data to the device. To perform a Block Erase, an opcode of
50H must be loaded into the device, followed by five
reserved bits, seven address bits (PA9-PA3), and 12 don’t
care bits. The seven address bits are used to specify which
block of eight pages is to be erased. When a low-to-high
transition occurs on the CS pin, the part will erase the
selected block of eight pages to 1s. The erase operation is
internally self-timed and should take place in a maximum
time of tBE. During this time, the status register will indicate
that the part is busy.
5
5 Page 
DC Characteristics
Symbol
ISB
ICC1
ICC2
ILI
ILO
VIL
VIH
VOL
VOH1
VOH2
Parameter
Standby Current
Active Current, Read
Operation
Active Current,
Program/Erase Operation
Input Load Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Condition
CS, RESET, WP = VCC, all inputs
at CMOS levels
f = 15 MHz; IOUT = 0 mA;
VCC = 5.5V
VCC = 5.5V
VIN = CMOS levels
VI/O = CMOS levels
IOL = 2.1 mA
IOH = -400 µA
IOH = -100 µA; VCC = 4.5V
AC Characteristics
Symbol
fSCK
fCAR
fBAR
tWH
tWL
tCS
tCSS
tCSH
tCSB
tSU
tH
tHO
tDIS
tV
tBRBD
tXFR
tEP
tP
tPE
tBE
tRST
tREC
Parameter
SCK Frequency
SCK Frequency for Continuous Array Read
SCK Frequency for Burst Array Read
SCK High Time
SCK Low Time
Minimum CS High Time
CS Setup Time
CS Hold Time
CS High to RDY/BUSY Low
Data In Setup Time
Data In Hold Time
Output Hold Time
Output Disable Time
Output Valid
Burst Read Boundary Delay
Page to Buffer Transfer/Compare Time
Page Erase and Programming Time
Page Programming Time
Page Erase Time
Block Erase Time
RESET Pulse Width
RESET Recovery Time
AT45D021A
Min Typ Max Units
10 20 µA
15 25 mA
25 50 mA
10 µA
10 µA
0.8 V
2.0 V
0.45 V
2.4 V
4.2 V
Min Max Units
15 MHz
10 MHz
15 MHz
30 ns
30 ns
250 ns
250 ns
250 ns
200 ns
10 ns
15 ns
0 ns
20 ns
25 ns
1 µs
150 µs
20 ms
14 ms
8 ms
12 ms
10 µs
1 µs
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AT45D021A.PDF ] | |
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