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PDF ATMEGA406 Data sheet ( Hoja de datos )
| Número de pieza | ATMEGA406 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 124 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS Throughput at 1 MHz
• Nonvolatile Program and Data Memories
– 40K Bytes of In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase
Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 bytes EEPROM, Endurance: 100,000 Write/Erase Cycles
– 2K Bytes Internal SRAM
– Programming Lock for Software Security
• On-chip Debugging
– Extensive On-chip Debug Support
– Available through JTAG interface
• Battery Management Features
– Two, Three, or Four Cells in Series
– Deep Under-voltage Protection
– Over-current Protection (Charge and Discharge)
– Short-circuit Protection (Discharge)
– Integrated Cell Balancing FETs
– High Voltage Outputs to Drive Charge/Precharge/Discharge FETs
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler, Compare Mode, and PWM
– One 16-bit Timer/Counter with Separate Prescaler and Compare Mode
– 12-bit Voltage ADC, Eight External and Two Internal ADC Inputs
– High Resolution Coulomb Counter ADC for Current Measurements
– TWI Serial Interface for SM-Bus
– Programmable Wake-up Timer
– Programmable Watchdog Timer
• Special Microcontroller Features
– Power-on Reset
– On-chip Voltage Regulator
– External and Internal Interrupt Sources
– Four Sleep Modes: Idle, Power-save, Power-down, and Power-off
• Packages
– 48-pin LQFP
• Operating Voltage: 4.0 - 25V
• Maximum Withstand Voltage (High-voltage pins): 28V
• Temperature Range: -30°C to 85°C
– Speed Grade: 1 MHz
8-bit
Microcontroller
with 40K Bytes
In-System
Programmable
Flash
ATmega406
Preliminary
2548F–AVR–03/2013
1 page  
ATmega406
2.2 Pin Descriptions
2.2.1 VFET
High voltage supply pin. This pin is used as supply for the internal voltage regulator, described in
”Voltage Regulator” on page 114. In addition the voltage level on this pin is monitored by the bat-
tery protection circuit, for deep-under-voltage protection. For details, see ”Battery Protection” on
page 125.
2.2.2 VCC
Digital supply voltage. Normally connected to VREG.
2.2.3 VREG
Output from the internal Voltage Regulator. Used for external decoupling to ensure stable regu-
lator operation. For details, see ”Voltage Regulator” on page 114.
2.2.4 VREF
Internal Voltage Reference for external decoupling. For details, see ”Voltage Reference and
Temperature Sensor” on page 121.
2.2.5
VREFGND
Ground for decoupling of Internal Voltage Reference. For details, see ”Voltage Reference and
Temperature Sensor” on page 121.
2.2.6 GND
Ground
2.2.7 SGND
Signal ground pin, used as reference for Voltage-ADC conversions. For details, see ”Voltage
ADC – 10-channel General Purpose 12-bit Sigma-Delta ADC” on page 116.
2.2.8
Port A (PA7:PA0)
PA3:PA0 serves as the analog inputs to the Voltage A/D Converter.
Port A also serves as a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega406 as listed in ”Alter-
nate Functions of Port A” on page 68.
2.2.9
Port B (PB7:PB0)
Port B is a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega406 as listed in ”Alter-
nate Functions of Port B” on page 70.
2548F–AVR–03/2013
5
5 Page 
ATmega406
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the ”AVR Instruc-
tion Set” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the ”AVR Instruction
Set” for detailed information.
5.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 5-2. AVR CPU General Purpose Working Registers
General
Purpose
Working
Registers
70
R0
R1
R2
…
R13
R14
R15
R16
R17
…
R26
R27
R28
R29
R30
R31
Addr.
0x00
0x01
0x02
0x0D
0x0E
0x0F
0x10
0x11
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 5-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
2548F–AVR–03/2013
11
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| PDF Descargar | [ Datasheet ATMEGA406.PDF ] | |
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