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PDF ATR2820 Data sheet ( Hoja de datos )
| Número de pieza | ATR2820 | |
| Descripción | Low IF WDCT 5.8 GHz Transceiver | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 5.8 GHz Transceiver
• 5 dBm TX Output Power
• –97 dBm Sensitivity
• 1152 kBit/s Data-rate
• Supply-voltage Range 2.9V to 3.6V
• Low IF Receiver
• Low Current Consumption
• Few Low Cost External Components
• No Mechanical Adjustment Required
• Small 32 pin 5 mm × 5 mm QFN Package
Applications
• 5.8 GHz Digital Cordless Phones
• Game Controllers
• Wireless Head Set
• FCC Part 15 Compliant Radio Link
Low IF WDCT
5.8 GHz
Transceiver
ATR2820
1. Description
The ATR2820 is a single chip RF-transceiver for applications in the 5.8 GHz ISM
band. The QFN32 packaged IC is a complete transceiver including image rejection
mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, integrated PLL with fully
integrated VCO. No mechanical adjustment is necessary in production.
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Preliminary
4704D–DECT–11/06
1 page  
Table 2-2. Pin Description Input/Output Circuits
Pin Symbol Function
ATR2820 [Preliminary]
Configuration
8 IREF External resistor for bias circuit
8
9 NC Not connected
10 VS_SYND Supply voltage for digital part of the PLL
11
VS_SYNA
Supply voltage for analog part of the
PLL
12
I_COMP
External resistor for compensation
current reference
12
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13
VS_VREG
Supply voltage for VCO voltage
regulator
14
CP/VT
Charge-pump output / VCO tuning
voltage input
14
4704D–DECT–11/06
5
5 Page 
ATR2820 [Preliminary]
3.7.4
Table 3-4.
D4
0
0
0
...
1
1
1
Swallow Counter Bits D0-D4
SC (Swallow Counter)
D3 D2 D1
000
000
001
... ... ...
110
111
111
D0
0
1
0
...
1
0
1
SSC
0
1
2
...
29
30
31
TX Mode ON/OFF
The TX bit is used to prepare the ATR2820 for a TX or RX slot. The transmit or receive mode is
later activated by the TX_ON respectively RX_ON signal.
3.7.5
Table 3-5. With Bit D9
D9
0
1
TRX
RX
TX
Data Recovery
The DR bit switches the interwnwaw.Dl adtaSahteaet4Ur.ecocmovery circuit on.
Table 3-6. With Bit D13
D13
0
1
Data Recovery
off
on
3.7.6
TX_ON / RX_ON Delay for Enhanced Interface Mode
The DELAY bits set the internal delay time. The delay counter is starting with the ENABLE high
edge at the end of the programming.
Delay Time: TDelay = DELAY × 2.315 µs
The minimum delay time is 70 µs, which corresponds to a Delay value of 31.
Table 3-7. Delay Setting
D23 D22 D21 D20 D19 D18 D17 D16 DELAY
0 0 0 1 1 1 1 1 31
0 0 1 0 0 0 0 1 32
...
1 1 1 1 1 1 1 0 254
1 1 1 1 1 1 1 1 255
4704D–DECT–11/06
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ATR2820.PDF ] | |
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