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PDF AT86RF230 Data sheet ( Hoja de datos )
| Número de pieza | AT86RF230 | |
| Descripción | Transceiver | |
| Fabricantes | ATMEL Corporation | |
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Features
• Fully Integrated 2.4 GHz-band Transceiver
• -101 dBm Receiver Sensitivity
• Low Current Consumption (Typical Values)
− SLEEP = 0.1 µA
− TRX_OFF = 1.7 mA
− RX_ON = 16 mA
− BUSY_TX = 17 mA (max. PTX)
• Power Supply Range 1.8V – 3.6V
− Internal LDO Voltage Regulators
− Battery Monitor
• SPI Slave Interface
• Baseband Signal Processing Compliant with IEEE 802.15.4
− SFD Detection, Spreading/De-spreading, Framing
− 128-byte FIFO for TRX
• Integrated Crystal Oscillator, 16 MHz
• Digital RSSI Register, 5-bit Value
• Fast Power-up Time < 1 msec
• Programmable TX Output Power from -17 dBm up to 3 dBm
• Integrated LNA
• Low External Component Count
− Antenna
− Reference Crystal
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− De-coupling Capacitors
• Integrated TX/RX Switch
• Integrated PLL Loop Filter
• Automatic VCO and Filter Calibration
• 32-pin Low-profile Lead-free Plastic QFN Package 5 mm x 5 mm x 0.9 mm
• Compliant to EN 300 440/328, FCC-CFR-47 Part 15
• Compliant to IEEE 802.15.4
ZigBee™/IEEE
802.15.4-
Transceiver
AT86RF230
Applications
• 802.15.4 Transceiver
• Transceiver for ZigBee System Solutions
Description
The AT86RF230 is a low-power 2.4 GHz transceiver specially designed for low
cost ZigBee/IEEE802.15.4 applications. The AT86RF230 is a true SPI-to-
antenna solution. All RF-critical components except the antenna, crystal and de-
coupling capacitors are integrated on-chip.
5131A-ZIGB-06/14/06
1 page  
2. General Circuit Description
AT86RF230
AVREG
BATMON
Analog Domain
TX power
control
FTN
XOSC
DCLK
Digital Domain
DVREG
IRQ
RFP
RFN
LNA
I
PPF
Q
PA
BPF
Frequency
Synthesis
TX Data
Limiter
ADC
TX BBP
Control Logic/
Configuration
Registers
RX BBP
TRX Data
Buffer
AGC
RSSI
5
SPI
Slave
Interface
SEL
MISO
SCLK
MOSI
CLKM
SLP_TR
RSTN
Figure 2-1.
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Block Diagram of AT86RF230
This single-chip RF transceiver provides a complete radio interface between the antenna and the micro-controller.
It comprises the analog radio part, digital demodulation including time and frequency synchronization and data
buffering. The number of external components is minimized so that only the antenna, the crystal and four
decoupling capacitors are required. The bidirectional differential antenna pins are used in common for RX and TX,
so no external antenna switch is needed.
The transceiver block diagram is shown in Figure 2-1. The receiver path is based on a low-IF topology. The
channel filter consists of three single side-band active RC resonators forming a 2 MHz band-pass filter with a
Butterworth characteristic centered at 2 MHz. Two 1st-order high-pass filters were added to the signal path to
achieve capacitive coupling at the single side-band filter (SSBF) output to suppress DC offset and integrator
feedback at the limiter amplifier. The 3-stage limiter amplifier provides sufficient gain to overcome the DC offset of
the succeeding single channel ADC and generates a digital RSSI signal with 3 dB granularity. The low-IF signal is
sampled at 16 MHz with 1-bit resolution and applied to the digital signal processing part.
Direct VCO modulation is used to generate the transmit signal. The modulation scheme is offset-QPSK (O-QPSK)
with half-sine pulse shaping and 32-length block coding (spreading). This is equivalent to minimum shift keying
(MSK) when transforming the spreading code sequences appropriately. The modulation signal is applied to both
the VCO and the fractional-N PLL to ensure the coherent phase modulation required for demodulation as an O-
QPSK signal. The frequency-modulated LO signal is fed to the power amplifier.
Two on-chip low-dropout voltage regulators provide the analog and digital 1.8V supply. The SPI interface and the
control registers will retain their settings in SLEEP mode when the regulators are turned off. The RX and TX signal
processing paths are highly integrated and optimized for low power consumption.
5131A-ZIGB-06/14/06
5
5 Page 
AT86RF230
4. Basic Operating Modes
This section summarizes all features that are needed to provide the basic functionality of a transceiver system,
such as receiving and transmitting frames, and powering down. These basic operating modes are sufficient for
ZigBee applications and are shown in Figure 4-1.
P_ON
(Power-on after VDD)
XOSC=ON
Pull=ON
SLEEP
(Sleep Mode)
XOSC=OFF
Pull=OFF
3
FORCE_TRX_OFF 12
(all modes except SLEEP)
12
TRX_OFF
(Clock Mode)
XOSC=ON
Pull=OFF
13 RST=0
(all modes except P_ON)
75
64
BUSY_RX
(Receive Mode)
CLKM=ON
Frame
Start
Frame
End
RX_ON
(Rx Listen Mode)
CLKM=ON
8 RX_ON
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PLL_ON 9
RX_ON_NOCLK
(Rx Listen Mode)
CLKM=OFF
SLP_STLRP=_1TR=0
PLL_ON
(PLL Mode)
11
Frame
End
10
TX_START
SLP_TR=1
BUSY_TX
(Transmit Mode)
Legend:
Blue: SPI Write to Register TRX_STATE (0x02)
Red: Control signals via IC Pin
Green: Event
Figure 4-1. Basic Operating Modes State Diagram
4.1. Configuration
The operating modes are controlled by two signal pins and the SPI access to register 0x02 (TRX_STATE). The
successful state change can be confirmed by reading the transceiver state from register 0x01 (TRX_STATUS).
The pin SLP_TR is used to enter SLEEP mode where current consumption is minimal (leakage current only) and to
wake-up the transceiver.
The pin RST provides a reset of all registers and forces the transceiver into TRX_OFF mode, if the IC is not in the
P_ON mode.
5131A-ZIGB-06/14/06
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT86RF230.PDF ] | |
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