PDF AT32AP7001 Data sheet ( Hoja de datos )

Número de pieza	AT32AP7001
Descripción	32-bit Microcontroller
Fabricantes	ATMEL Corporation
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No Preview Available ! Features • High Performance, Low Power AVR®32 32-Bit Microcontroller – 210 DMIPS throughput at 150 MHz – 16 KB instruction cache and 16 KB data caches – Memory Management Unit enabling use of operating systems – Single-cycle RISC instruction set including SIMD and DSP instructions – Java Hardware Acceleration • Multimedia Co-Processor – Vector Multiplication Unit for video acceleration through color-space conversion (YUV<->RGB), image scaling and filtering, quarter pixel motion compensation • Multi-hierarchy bus system – High-performance data transfers on separate buses for increased performance • Data Memories – 32KBytes SRAM • External Memory Interface – SDRAM, DataFlash™, SRAM, Multi Media Card (MMC), Secure Digital (SD), – Compact Flash, Smart Media, NAND Flash • Direct Memory Access Controller – External Memory access without CPU intervention • Interrupt Controller – Individually maskable Interrupts – Each interrupt request has a programmable priority and autovector address • System Functions – Power and Clock Manager – Crystal Oscillator with Phase-Lock-Loop (PLL) – Watchdog Timer – Real-time Clock • 6 Multifunction timer/counters – Three external clock inputs, I/O pins, PWM, capture and various counting www.DataSheet4U.com capabilities • 4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – 115.2 kbps IrDA Modulation and Demodulation – Hardware and software handshaking • 3 Synchronous Serial Protocol controllers – Supports I2S, SPI and generic frame-based protocols • Two-Wire Interface – Sequential Read/Write Operations, Philips’ I2C© compatible • Image Sensor Interface – 12-bit Data Interface for CMOS cameras • Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device – On-chip Transceivers with physical interface • 16-bit stereo audio DAC – Sample rates up to 50 kHz • On-Chip Debug System – Nexus Class 3 – Full speed, non-intrusive data and program trace – Runtime control and JTAG interface • Package/Pins – AT32AP7001: 208-pin QFP/ 90 GPIO pins • Power supplies – 1.65V to1.95V VDDCORE – 3.0V to 3.6V VDDIO AVR®32 32-bit Microcontroller AT32AP7001 Preliminary 32015A-AVR32-02/07 1 page AT32AP7001 Table 2-1. Signal Description List Signal Name Function Type Active Level Comments NWAIT External Wait Signal Input Low NWE0 Write Enable 0 Output Low NWE1 Write Enable 1 Output Low NWE3 Write Enable 3 Output Low RAS Row Signal Output Low SDA10 SDRAM Address 10 Line Output SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output SDCS SDRAM Chip Select Output Low SDWE SDRAM Write Enable Output Low Image Sensor Interface - ISI DATA0 - DATA11 Image Sensor Data Input HSYNC Horizontal Synchronization Input PCLK Image Sensor Data Clock Input VSYNC Vertical Synchronization Input Mulitmedia Card Interface - MMCI CLK Multimedia Card Clock Output CMD0 - CMD1 Multimedia Card Command I/O DATA0 - DATA7 Multimedia Card Data I/O Parallel Input/Output 2 - PIOA, PIOB, PIOC, PIOD, PIOE PA0 - PA31 Parallel I/O Controller PIOA I/O PB0 - PB30 Parallel I/O Controller PIOB I/O PC0 - PC31 Parallel I/O Controller PIOC I/O PD0 - PD17 Parallel I/O Controller PIOD I/O PE0 - PE26 Parallel I/O Controller PIOE I/O PS2 Interface - PSIF CLOCK0 - CLOCK1 PS2 Clock Input DATA0 - DATA1 PS2 Data I/O 32015A-AVR32-02/07 5 5 Page AT32AP7001 5. Blockdiagram Figure 5-1. Blockdiagram TRST_N TCK TDO TDI TMS JTAG INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N NEXUS CLASS 3 OCD AP CPU MEMORY MANAGEMENT UNIT INSTR CACHE DATA CACHE PIXEL COPROCESSOR D+ USB D- INTERFACE DATA[11..0] HSYNC VSYNC PCLK DMA IMAGE SENSOR INTERFACE INTRAM0 INTRAM1 S M M M S S MMS M HIGH SPEED BUS MATRIX S M S M RAS, CAS, SDWE, NANDOE, NANDWE, SDCK, SDCKE, NWE3, NWE1, NWE0, NRD, NCS[3,1,0], ADDR[22..0] CONFIGURATION REGISTERS BUS DATA[15..0] PB HSB HSB-PB BRIDGE B DMA CONTROLLER HSB HSB-PB BRIDGE A PB HSB-HSB BRIDGE PERIPHERAL DMA CONTROLLER NWAIT SDCS, NCS[5,4,2] CFRNW, CFCE1, CFCE2, ADDR[23..25] DATA[31..16] PA PB DATA0 PC PD DATA1 AUDIO BITSTREAM PE DATA0N DAC DATA1N CLK CMD DATA[7..0] MULTIMEDIA CARD INTERFACE USART0 USART1 USART2 USART3 SERIAL PERIPHERAL INTERFACE 0/1 RXD TXD CLK RTS, CTS SCK MISO, MOSI NPCS0 NPCS[3..1] SCLK SDI SSYNC SDO AC97 CONTROLLER SYNCHRONOUS SERIAL CONTROLLER 0/1/2 TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA XIN32 XOUT32 32 KHz OSC XIN0 XOUT0 OSC0 XIN1 XOUT1 PLL0 OSC1 PLL0 PLL1 PLL1 GCLK[3..0] OSCEN_N RESET_N POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER TWO-WIRE INTERFACE PS2 INTERFACE REAL TIME COUNTER WATCHDOG TIMER SCL SDA CLOCK[1..0] DATA[1..0] PA PB PC PD PE A[2..0] B[2..0] CLK[2..0] EXTINT[7..0] KPS[7..0] NMI_N TIMER/COUNTER 0/1 EXTERNAL INTERRUPT CONTROLLER INTERRUPT CONTROLLER PULSE WIDTH MODULATION CONTROLLER PWM0 PWM1 PWM2 PWM3 32015A–AVR32–02/07 11 11 Page

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