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PDF ATTINY15L Data sheet ( Hoja de datos )
| Número de pieza | ATTINY15L | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 1K Byte In-System Programmable Flash Program Memory
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program Data Security
• Peripheral Features
– Interrupt and Wake-up on Pin Change
– Two 8-bit Timer/Counters with Separate Prescalers
– One 150 kHz, 8-bit High-speed PWM Output
– 4-channel 10-bit ADC
One Differential Voltage Input with Optional Gain of 20x
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
• Special Microcontroller Features
– In-System Programmable via SPI Port
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal, Calibrated 1.6 MHz Tunable Oscillator
– Internal 25.6 MHz Clock Generator for Timer/Counter
– External and Internal Interrupt Sources
– Low-power Idle and Power-down Modes
• Power Consumption at 1.6 MHz, 3V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down: < 1 µA
• I/O and Packages
– 8-lead PDIP and 8-lead SOIC: 6 Programmable I/O Lines
• Operating Voltages
– 2.7V - 5.5V
• Internal 1.6 MHz System Clock
Pin Configuration
PDIP/SOIC
(RESET/ADC0) PB5
(ADC3) PB4
(ADC2) PB3
GND
1
2
3
4
8 VCC
7 PB2 (ADC1/SCK/T0/INT0)
6 PB1 (AIN1/MISO/OC1A)
5 PB0 (AIN0/AREF/MOSI)
8-bit
Microcontroller
with 1K Byte
Flash
ATtiny15L
Not recommended for new
design
Rev. 1187H–AVR–09/07
1
1 page  
ATtiny15L
Architectural
Overview
1187H–AVR–09/07
ATtiny15L
The fast-access Register File concept contains 32 x 8-bit general purpose working reg-
isters with a single-clock-cycle access time. This means that during one single clock
cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output
from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This
pointer is called the Z-pointer, and can address the Register File, IO file and the Flash
Program memory.
Figure 2. The ATtiny15L AVR RISC Architecture
Data Bus 8-bit
512 x 16
Program
FLASH
Program
Counter
Status
and Test
Control
Registrers
Interrupt
Unit
Instruction
Register
Direct Addressing
Instruction
Decoder
Control Lines
32 x 8
General
Purpose
Registrers
ALU
SPI Unit
2 x 8-bit
Timer/Counter
Watchdog
Timer
ADC
64 x 8
EEPROM
Analog
Comparator
I/O Lines
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single-register operations are also executed in the ALU. Figure 2
shows the ATtiny15L AVR RISC microcontroller architecture. The AVR uses a Harvard
architecture concept with separate memories and buses for program and data memo-
ries. The program memory is accessed with a two-stage pipeline. While one instruction
is being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed in every clock cycle. The Program memory
is In-System Programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly
accessed. All AVR instructions have a single 16-bit word format, meaning that every
program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is a 3-level-deep Hardware Stack dedicated for subrou-
tines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters and other I/O functions. The memory spaces in the AVR
architecture are all linear and regular memory maps.
5
5 Page 
ATtiny15L
The Status Register – SREG
Table 2. ATtiny15L I/O Space(1) (Continued)
Address Hex Name
Function
$06
ADCSR
ADC Control and Status Register
$05
ADCH
ADC Data Register High
$04
ADCL
ADC Data Register Low
Note: 1. Reserved and unused locations are not shown in the table.
All ATtiny15L I/O and peripheral registers are placed in the I/O space. The I/O locations
are accessed by the IN and OUT instructions transferring data between the 32 general
purpose working registers and the I/O space. I/O Registers within the address range
$00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these regis-
ters, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set chapter for more details. For compatibility with future
devices, reserved bits should be written zero if accessed. Reserved I/O memory
addresses should never be written.
The I/O and Peripheral Control Registers are explained in the following sections.
The AVR Status Register – SREG – at I/O space location $3F is defined as:
Bit
$3F
Read/Write
Initial Value
76543210
I THSVNZC
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in the Interrupt Mask Registers –
GIMSK and TIMSK. If the Global Interrupt Enable Register is cleared (zero), none of the
interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared
by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
ied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The Half-carry Flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-
ment Overflow Flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the Instruction Set description for detailed information.
1187H–AVR–09/07
11
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