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CS101 데이터시트 PDF




Fujitsu Media Devices에서 제조한 전자 부품 CS101은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CS101 자료 제공

부품번호 CS101 기능
기능 Standard Cell
제조업체 Fujitsu Media Devices
로고 Fujitsu Media Devices 로고


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CS101 데이터시트, 핀배열, 회로
FUJITSU SEMICONDUCTOR
DATA SHEET
DS06-20210-2E
Semicustom
CMOS
Standard Cell
CS101 Series
DESCRIPTION
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power
consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three
types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use.
As well as providing a maximum of 100 million gates, approximately twice the level of integration achieved in
previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the high-
speed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
FEATURES
www.DataSheet4U.com
• Technology
: 90 nm Si gate CMOS
7- to 10-metal layers.
Low-K (low permittivity) material is used for all dielectric inter-layers.
Three different types of core transistors (low leak, standard, and high speed)
can be used on the same chip.
The design rules comply with industry standard processes.
• Power supply voltage
: +1.2 V ± 0.1 V (standard)
• Operation junction temperature : 40 °C to + 125 °C (standard)
• Gate delay time
: tpd = 12 ps (1.2 V, Inverter, F/O = 1)
• Gate power consumption
: Pd = 2.7 nW/MHz/BC (1.2 V, 2 NAND, F/O = 1)
• High level of integration
: Up to 91 million gates
• Reduced chip sized realized by I/O with pad.
• Support for a wide range of cell sets (from low power versions to ultra high speed versions).
• Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incorpo-
rated.
• Compiled cell (RAM, ROM, others)
• Support for ultra high speed (up to 10 Gbps) interface macros.
• Special interfaces (LVDS, SSTL2, etc.)
• Supports use of industry standard libraries (.LIB).
• Uses industry standard tools and supports the optimum tools for the application.
(Continued)




CS101 pdf, 반도체, 판매, 대치품
CS101 Series
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Application
Power supply voltage
Input voltage *1
Output voltage
Storage temperature
Operation junction
temperature
Power supply pin
current *2
Output current *3
VDD
VI
VO
Tstg
VDDI (Internal)
VDDE (External 2.5 V)
VDDE (External 3.3 V)
1.2 V
2.5 V
3.3 V
1.2 V
2.5 V
3.3 V
Plastic package
Tj
ID
per VDD, VDDI, VDDE
VSS pin
IO
*1 : The values vary depending on the type of macros.
*2 : Maximum power supply current that can steadily flow.
*3 : Maximum output current that can steadily flow.
*4 : Contact your Fujitsu representative for details.
Note : VSS = 0 V
Min
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
55
40
Rating
Max
+ 1.8
+ 3.6
+ 4.6
VDDI + 0.5 ( 1.8)
VDDE + 0.5 ( 3.6)
VDDE + 0.5 ( 4.6)
VDDI + 0.5 ( 1.8)
VDDE + 0.5 ( 3.6)
VDDE + 0.5 ( 4.6)
+ 125
Unit
V
V
V
V
V
V
V
V
V
°C
+ 125
°C
*4 mA
*4 mA
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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CS101 전자부품, 판매, 대치품
CS101 Series
AC Characteristics (with low power consumption, high density CS101SL library used)
Parameter
Symbol
Min
Value
Typ
Delay time
tpd *1
typ *2 × tmin *3 typ *2 × ttyp *3
*1 : Delay time = propagation delay time, enable time, disable time
*2 : “typ” is calculated based on the cell specifications.
*3 : Measurement condition
Measurement condition
tmin
VDD = 1.2 V ± 0.1 V, VSS = 0 V, Tj = − 40 °C to +125 °C
0.62
Max
typ *2 × tmax *3
ttyp
1.00
Unit
ns
tmax
1.57
I/O Pin Capacitance
Parameter
Symbol
Value
Input pin
CIN
Max16
Output pin
COUT
Max16
I/O pin
CI/O
Max16
Note : The capacitance values vary depending on the package and pin positions.
Unit
pF
pF
pF
DESIGN METHODS
Fujitsu’s Reference Design Flow provides the following functions that help shorten the development time of large
scale and high quality LSIs.
• High reliability design estimation in the early stage of physical design realized by physical prototyping.
• Layout synthesis with optimized timing realized by physical synthesis tools.
• High accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and
crosstalk.
• I/O design environment (power line design, assignment and selection of I/Os, package selection) considering
noise.
PACKAGES
Packages available for existing series can be used for CS101 series. This allows smooth replacement with
previously developed products.
Please contact your Fujitsu agent for details of delivery times.
FBGA package : Max 424 pins
FC-BGA package : Max 2116 pins
PBGA package : Max 420 pins
TEBGA package : Max 900 pins
(Packages under planning are included.)
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