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AT25128A 데이터시트 PDF




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부품번호 AT25128A 기능
기능 (AT25128A / AT25256A) SPI Serial EEPROMs
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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AT25128A 데이터시트, 핀배열, 회로
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
20 MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (5 ms Max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
Automotive Grade, Extended Temperature and Lead-free/Halogen-free
Devices Available
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and
8-lead SAP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Die
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable
programmable read only memory (EEPROM) organized as 16,384/32,768 words of
8 bits each. The device is optimized for use in many industrial and commercial appli-
cations where low-power and low-voltage operation are essential. The devices are
available in space saving 8-lead PDIP, 8-lead EIAJwwwS.DOataISChee,t48U.c-olmead JEDEC SOIC, 8-
lead TSSOP, 8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is
available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128A
AT25256A
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via
a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
8-lead PDIP
8-lead SOIC
Table 1. Pin Configurations
Pin Name
Function
CS Chip Select
CS
SO
WP
GND
1
2
3
4
8 VCC
CS 1
7 HOLD SO 2
6 SCK
WP 3
5 SI
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
SCK
SI
SO
GND
VCC
WP
HOLD
NC
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
8-lead TSSOP
8-lead SAP
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
8-ball dBGA2 Bottom View
VCC
HOLD
SCK
SI
8
7
6
5
1 CS
2 SO
3 WP
4 GND
Bottom View
3368H–SEEPR–8/05
1




AT25128A pdf, 반도체, 판매, 대치품
Table 4. AC Characteristics (Continued)
Applicable over recommended operating range from TAI = 40°C to + 85°C, TAE = 40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min Max Units
tWL SCK Low Time
4.55.5
2.75.5
1.85.5
20
40
80
ns
tCS CS High Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tCSS CS Setup Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tCSH CS Hold Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tSU Data In Setup Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tH Data In Hold Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tHD Hold Setup Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tCD Hold Hold Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tV Output Valid
4.55.5
2.75.5
1.85.5
0 20
0 40 ns
0 80
tHO Output Hold Time
4.55.5
2.75.5
1.85.5
0
0
0
ns
tLZ Hold to Output Low Z
4.55.5
2.75.5
1.85.5
0 25
0 50 ns
0 100
tHZ Hold to Output High Z
4.55.5
2.75.5
1.85.5
25
50 ns
100
tDIS Output Disable Time
4.55.5
2.75.5
1.85.5
25
50 ns
100
tWC Write Cycle Time
4.55.5
2.75.5
1.85.5
5
5
5
Endurance(1) 5.0V, 25°C, Page Mode
1M
Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
ms
Write Cycles
4 AT25128A/256A
3368H–SEEPR–8/05

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AT25128A 전자부품, 판매, 대치품
Functional
Description
3368H–SEEPR–8/05
AT25128A/256A
The AT25128A/256A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.
The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in see Table 5. All instructions, addresses, and data
are transferred with the MSB first and start with a high-to-low CS transition.
Table 5. Instruction Set for the AT25128A/256A
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The Ready/Busy and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6. Status Register Format
Bit 7
Bit 6
Bit 5
WPEN
X
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 7. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is not write enabled. Bit 1 = “1” indicates
the device is write enabled.
Bit 2 (BP0)
See Table 8 on page 8.
Bit 3 (BP1)
See Table 8 on page 8.
Bits 4 6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 9 on page 8.
Bits 0 7 are “1”s during an internal write cycle.
7

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