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PDF AT25256A Data sheet ( Hoja de datos )
| Número de pieza | AT25256A | |
| Descripción | (AT25128A / AT25256A) SPI Serial EEPROMs | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Data Sheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• 20 MHz Clock Rate (5V)
• 64-byte Page Mode and Byte Write Operation
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
• Self-timed Write Cycle (5 ms Max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
• Automotive Grade, Extended Temperature and Lead-free/Halogen-free
Devices Available
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and
8-lead SAP Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Die
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable
programmable read only memory (EEPROM) organized as 16,384/32,768 words of
8 bits each. The device is optimized for use in many industrial and commercial appli-
cations where low-power and low-voltage operation are essential. The devices are
available in space saving 8-lead PDIP, 8-lead EIAJwwwS.DOataISChee,t48U.c-olmead JEDEC SOIC, 8-
lead TSSOP, 8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is
available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128A
AT25256A
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via
a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
8-lead PDIP
8-lead SOIC
Table 1. Pin Configurations
Pin Name
Function
CS Chip Select
CS
SO
WP
GND
1
2
3
4
8 VCC
CS 1
7 HOLD SO 2
6 SCK
WP 3
5 SI
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
SCK
SI
SO
GND
VCC
WP
HOLD
NC
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
8-lead TSSOP
8-lead SAP
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
8-ball dBGA2 Bottom View
VCC
HOLD
SCK
SI
8
7
6
5
1 CS
2 SO
3 WP
4 GND
Bottom View
3368H–SEEPR–8/05
1
1 page  
Serial Interface
Description
AT25128A/256A
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25128A/256A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25128A/256A in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
3368H–SEEPR–8/05
5
5 Page 
AT25128A/256A
Figure 6. RDSR Timing
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SI INSTRUCTION
HIGH IMPEDANCE
SO
Figure 7. WRSR Timing
DATA OUT
76543210
MSB
Figure 8. READ Timing
3368H–SEEPR–8/05
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AT25256A.PDF ] | |
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