Datasheet.kr   

AT45DB642D 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT45DB642D은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AT45DB642D 자료 제공

부품번호 AT45DB642D 기능
기능 64-megabit 2.7-volt Dual-interface DataFlash
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


AT45DB642D 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

AT45DB642D 데이터시트, 핀배열, 회로
Features
Single 2.7V - 3.6V Supply
Dual-interface Architecture
– RapidS Serial Interface: 66 MHz Maximum Clock Frequency
SPI Compatible Modes 0 and 3
– Rapid8 8-bit Interface: 50 MHz Maximum Clock Frequency
User Configurable Page Size
– 1024 Bytes per Page
– 1056 Bytes per Page
– Page Size Can Be Factory Pre-configured for 1024 Bytes
Page Program Operation
– Intelligent Programming Operation
– 8192 Pages (1024/1056 Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (1 Kbyte)
– Block Erase (8 Kbytes)
– Sector Erase (256 Kbytes)
– Chip Erase (64 Mbits)
Two SRAM Data Buffers (1024/1056 Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 10 mA Active Read Current Typical – Serial Interface
– 10 mA Active Read Current Typical – 8-bit Interface
– 25 µA Standby Current Typical
– 15 µA Deep Power Down Typical
Hardware and Software Data Protection Features
– Individual Sector
Permanent Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
Temperature Range
– Industrial: -40°C to +85°C
64-megabit
2.7-volt
Dual-interface
DataFlash®
AT45DB642D
3542K–DFLASH–04/09




AT45DB642D pdf, 반도체, 판매, 대치품
Table 2-1.
Symbol
SER/BYTE
Pin Configurations (Continued)
Name and Function
Serial/8-bit Interface Control: The DataFlash may be configured to utilize either its serial port or
8-bit port through the use of the serial/8-bit control pin (SER/BYTE). When the SER/BYTE pin is
held high, the serial port (SI and SO) of the DataFlash will be used for all data transfers, and the
8-bit port (I/O7 - I/O0) will be in a high impedance state. Any data presented on the 8-bit port
while SER/BYTE is held high will be ignored. When the SER/BYTE is held low, the 8-bit port will
be used for all data transfers, and the SO pin of the serial port will be in a high impedance state.
While SER/BYTE is low, any data presented on the SI pin will be ignored. Switching between the
serial port and 8-bit port should only be done while the CS pin is high and the device is not busy
in an internally self-timed operation.
The SER/BYTE pin is internally pulled high; therefore, if the 8-bit port is never to be used, then
connection of the SER/BYTE pin is not necessary. In addition, if the SER/BYTE pin is not
connected or if the SER/BYTE pin is always driven high externally, then the 8-bit input/output pins
(I/O7-I/O0), the VCCP pin, and the GNDP pin should be treated as “no connect”.
Asserted
State
Low
Type
Input
VCC
GND
VCCP
GNDP
Device Power Supply: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
Ground: The ground reference for the power supply. GND should be connected to the system
ground.
– Power
– Ground
8-bit Port Supply Voltage: The VCCP pin is used to supply power for the 8-bit input/output pins
(I/O7-I/O0). The VCCP pin needs to be used if the 8-bit port is to be utilized; however, this pin
should be treated as “no connect” if the SER/BYTE pin is not connected or if the SER/BYTE pin is
Power
always driven high externally.
8-bit Port Ground: The GNDP pin is used to provide ground for the 8-bit input/output pins (I/O7-
I/O0). The GNDP pin needs to be used if the 8-bit port is to be utilized; however, this pin should
be treated as “no connect” if the SER/BYTE pin is not connected or if the SER/BYTE pin is
– Ground
always driven high externally.
Figure 2-1. TSOP Top View: Type 1
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK/CLK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 NC
27 NC
26 I/O7
25 I/O6
24 I/O5
23 I/O4
22 VCCP
21 GNDP
20 I/O3
19 I/O2
18 I/O1
17 I/O0
16 SER/BYTE
15 NC
Figure 2-2. BGA Package Ball-Out (Top View)
12 3 4 5
A
NC NC NC NC
B
NC SCK GND VCC NC
C
NC CS RDY/BSY WP NC
D
NC SO
SI RESET NC
E
NC NC NC NC NC
Figure 2-3.
CASON Top View through Package
SI 1
SCK 2
RESET 3
CS 4
8 SO
7 GND
6 VCC
5 WP
4 AT45DB642D
3542K–DFLASH–04/09

4페이지










AT45DB642D 전자부품, 판매, 대치품
AT45DB642D
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one page
to the beginning of the next page). When the last bit (or byte if using the 8-bit interface mode) in
the main memory array has been read, the device will continue reading back at the beginning of
the first page of memory. As with crossing over page boundaries, no delays will be incurred
when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Continuous Array
Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both data buf-
fers and leaves the contents of the buffers unchanged.
6.2 Continuous Array Read (High Frequency Mode: 0BH): Up to 66 MHz
This command can be used with the serial interface to read the main memory array sequentially
in high speed mode for any clock frequency up to the maximum specified by fCAR1. To perform a
continuous read array with the page size set to 1056 bytes, the CS must first be asserted then
an opcode 0BH must be clocked into the device followed by three address bytes and a dummy
byte. The first 13 bits (PA12 - PA0) of the 24-bit address sequence specify which page of the
main memory array to read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence
specify the starting byte address within the page. To perform a continuous read with the page
size set to 1024 bytes, the opcode, 0BH, must be clocked into the device followed by three
address bytes (A22 - A0) and a dummy byte. Following the dummy byte, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous
Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both
data buffers and leaves the contents of the buffers unchanged.
6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHz
This command can be used with the serial interface to read the main memory array sequentially
without a dummy byte up to maximum frequencies specified by fCAR2. To perform a continuous
read array with the page size set to 1056 bytes, the CS must first be asserted then an opcode,
03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence). The first 13 bits (PA12 - PA0) of the 24-bit address sequence
specify which page of the main memory array to read, and the last 11 bits (BA10 - BA0) of the
24-bit address sequence specify the starting byte address within the page. To perform a contin-
uous read with the page size set to 1024 bytes, the opcode, 03H, must be clocked into the
device followed by three address bytes (A22 - A0). Following the address bytes, additional clock
pulses on the SCK pin will result in data being output on the SO (serial output) pin.
3542K–DFLASH–04/09
7

7페이지


구       성 총 30 페이지수
다운로드[ AT45DB642D.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
AT45DB642

64-megabit 2.7-volt Only Dual-interface DataFlash

ATMEL Corporation
ATMEL Corporation
AT45DB642D

64-megabit 2.7V Dual-interface DataFlash

Adesto
Adesto

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵