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AT89LP216 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT89LP216은 전자 산업 및 응용 분야에서
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부품번호 AT89LP216 기능
기능 8-bit Microcontroller
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AT89LP216 데이터시트, 핀배열, 회로
Features
8-bit Microcontroller Compatible with MCS®51 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 128 x 8 Internal RAM
– 4-level Interrupt Priority
Nonvolatile Program Memory
– 2K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: Minimum 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 64-byte User Signature Array
– 2-level Program Memory Lock for Software Security
Peripheral Features
– Two 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Programmable Watchdog Timer with Software Reset
– Analog Comparator with Selectable Interrupt and Debouncing
– 8 General-purpose Interrupt Pins
Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Internal 8 MHz RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
I/O and Packages
– Up to 14 Programmable I/O Lines
– Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
– 5V Tolerant I/O
– 16-lead TSSOP, SOIC or PDIP
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40C to 85°C Temperature Range
8-bit
Microcontroller
with 2K Bytes
Flash
AT89LP216
1. Description
The AT89LP216 is a low-power, high-performance CMOS 8-bit microcontroller with
2K bytes of In-System Programmable Flash memory. The device is manufactured
using Atmel®'s high-density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. The AT89LP216 is built around an
enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc-
tions to execute in 12, 24 or 48 clock cycles. In the AT89LP216 CPU, instructions
3621E–MICRO–11/10




AT89LP216 pdf, 반도체, 판매, 대치품
4. Block Diagram
Figure 4-1. AT89LP216 Block Diagram
Single Cycle
8051 CPU
2K Bytes
Flash
128 Bytes
RAM
Port 3
Configurable I/O
Port 1
Configurable I/O
General-purpose
Interrupt
CPU Clock
UART
SPI
Timer 0
Timer 1
Analog
Comparator
Watchdog
Timer
On-Chip
RC Oscillator
Configurable
Oscillator
Crystal or
Resonator
5. Comparison to Standard 8051
The AT89LP216 is part of a family of devices with enhanced features that are fully binary com-
patible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and
pin alternate functions are identical to Atmel’s existing standard 8051 products. However, due to
the high performance nature of the device, some system behaviors are different from those of
Atmel's standard 8051 products such as AT89S52 or AT89S2051. The differences from the
standard 8051 are outlined in the following paragraphs.
5.1 System Clock
The CPU clock frequency equals the external XTAL1 frequency. The oscillator is no longer
divided by 2 to provide the internal clock and x2 mode is not supported.
5.2 Instruction Execution with Single-cycle Fetch
The CPU fetches one code byte from memory every clock cycle instead of every six clock
cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer
executes instructions in 12 to 48 clock cycles. Each instruction executes in only 1 to 4 clock
cycles. See “Instruction Set Summary” on page 59 for more details.
4 AT89LP216
3621E–MICRO–11/10

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AT89LP216 전자부품, 판매, 대치품
AT89LP216
6.2 Data Memory
The AT89LP216 contains 128 bytes of general SRAM data memory plus 128 bytes of I/O mem-
ory mapped into a single 8-bit address space. The 128 bytes of data memory may be accessed
through both direct and indirect addressing of the lower 128 byte addresses. The 128 bytes of
I/O memory reside in the upper 128 byte address space (Figure 6-2). The I/O memory can only
be accessed through direct addressing and contains the Special Function Registers (SFRs).
Indirect accesses to the upper 128 byte addresses will return invalid data. The lowest 32 bytes
of data memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3
and PSW.4) select which register bank is in use. Instructions using register addressing will only
access the currently specified bank. The AT89LP216 does not support external data memory.
Figure 6-2. Data Memory Map
FFH
UPPE R
128
80H
7F H
LO WER
128
0
Accessible
By Direct
Addressing
Only
Accessible
By Direct
and Indirect
Addressing
Only
Special Function
Registers
Ports
Status and Control Bits
Timers
Registers
Stack Pointer
Accumulator
(Etc.)
3621E–MICRO–11/10
7

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