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PDF T83C5101 Data sheet ( Hoja de datos )
| Número de pieza | T83C5101 | |
| Descripción | (T83C5101x) 8-bit Low Pin Count Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 80C51 Code Compatible
– 8051 Instruction Compatible
– 16 I/O + 2 Outputs in 24 Pin Packages
16 I/O + 6 Outputs in 28 Pin Packages
– Three 16-bit Timer/Counters
– 256 Bytes Scratchpad RAM
• Program Memory
– 8 KB ROM T83C5102
– 16 KB ROM T83C5101
– 16 KB EPROM/OTP T87C5101
• High-speed Architecture
• 40 MHz from 2.7 to 5.5V, Commercial or Industrial Temperature Range:
– 40 MHz with a 40 MHz Crystal In Std. Mode
– 40 MHz with a 20 MHz Crystal In X2 Mode
• 66 MHz from 4.5 to 5.5V, Commercial Temperature Range
– 40 MHz with a 40 MHz Crystal in Std. Mode
– 66 MHz with a 33 MHz Crystal in X2 Mode
• Dual Data Pointer
• On-chip eXpanded RAM (XRAM) (256 bytes)
• Programmable Clock Out and Up/Down Timer/Counter 2
• Asynchronous Port Reset
• Interrupt Structure with
– 6 Interrupt Sources,
– 4-Level Priority Interrupt System
• Full-duplex Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
• Low EMI (no ALE)
• Power Control Modes
www.DataSheet4U.com
– Idle Mode
– Power-down Mode
• Packages: SO24, DIL24, SSOP24, SO28
8-bit Low Pin
Count
Microcontrollers
T83C5101
T87C5101
T83C5102
Description
The T8xC5101/02 family is a high performance CMOS ROM, OTP, EPROM derivative
of the 80C51 CMOS single chip 8-bit microcontroller.
The T8xC5101/02 family is a low pin count device where only Port 1, port 3 and 2/6
bits of a new port 4 are outputted. This prevents any external access, like external pro-
gram memory access (fetch, MOVC) or external data memory (MOVX). The
T8xC5101/02 family retains all features of the 80C51 with extended capacity 8 KB
ROM (5102), 16 KB ROM (5101)/16 KB EPROM/OTP (5101), 256 bytes of internal
RAM, a 6-source, 4-level interrupt system, an on-chip oscillator and three
timer/counters.
In addition, the T8xC5101/02 family has an XRAM of 256 bytes, the X2 feature, a
more versatile serial channel that facilitates multiprocessor communication (EUART),
a dual data pointer and an improved timer 2. The fully static design of the
T8xC5101/02 family allows to reduce system power consumption by bringing the
clock frequency down to any value, even DC, without loss of data.
The T8xC5101/02 family has 2 software-selectable modes of reduced activity for fur-
ther reduction in power consumption. In idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In power-down mode the
RAM is saved and all other functions are inoperative.
Rev. 4233G–8051–03/03
1
1 page  
T8xC5101/02
T8xC5101/02 Pin Configuration
P3.4/T0 1
P3.3/INT1 2
P3.2/INT0 3
P3.1 4
P3.0 5
VPP 6
P4.0/Prog 7
P4.1/Test 8
RST 9
XTAL2 10
XTAL1 11
Vss 12
24
23
22
21
DIL24
20
19
SO24 18
17
SSOP24* 16
15
14
13
Vcc
P3.5/T1
P3.6
P3.7
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2
* Check for availability
P3.4/T0 1
P3.3/INT1 2
P3.2/INT0 3
P3.1 4
P3.0 5
VPP 6
P4.3 7
P4.0/Prog 8
P4.1/Test 9
RST 10
XTAL2 11
XTAL1 12
P4.4 13
Vss 14
28 Vcc
27 P4.2
26 P3.5/T1
25 P3.6
24 P3.7
23 P1.7
SO28* 22 P1.6
21 P4.5
20 P1.5
19 P1.4
18 P1.3
17 P1.2
16 P1.1/T2EX
15 P1.0/T2
* Check for availability
Mnemonic
VSS
VCC
P1.0-P1.7
Pin Number
28
24 pins pins
12 14
24 28
13-20
15-20
22-23
P4.0 (Prog)-P4.1 7 8
(Test)
89
P4.2-P4.5
P3.0-P3.7
NA
5-1
23-21
27
7
13
21
5-1
26-24
55
44
33
22
Type
I
I
I/O
I/O
I
O (I)
O (I)
Name and Function
Ground: 0V reference
Power Supply: This is the power supply voltage for normal, idle and power-down operation
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1
also receives the low-order address byte during memory programming and verification.
Alternate functions for Port 1 include:
T2 (P1.0): Timer/Counter 2 external count input/Clockout
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
Port 4 bits 0 & 1: Except during programming and verifying, these two bits are output port driving
30 micro Amps at high level and sinking 10 mA at low level (Vol < 1V). If they have 1s written to
them, they output a high level and if they have 0 written to them, they output a low level. These 2
pins cannot be used as inputs. Users should take care to never externally drive these pins
low, especially during reset. These two pins are primarily designed to drive LEDs.
During programming and verifying, these two pins are used as input, as explained in the
corresponding chapter.
A Read or a Read/Modify/Write instruction to these bits will read the status of the output: 1 if the
output is 1, 0 if the output is 0.
Port 4 bits 2 to 5: bidirectional I/O port with internal pull-ups. Port 4.2 to 4.5 pins that have 1s
I/O written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
4.2 to 4.5 pins that are externally pulled low will source current because of the internal pull-ups.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3
also serves the special features of the 80C51 family, as listed below.
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt 0
I INT1 (P3.3): External interrupt 1
4233G–8051–03/03
5
5 Page 
Application
T8xC5101/02
Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search ...) are well
served by using one data pointer as a ’source’ pointer and the other one as a "destina-
tion" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1
; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1
; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR
; increment SOURCE address
000C 05A2 INC AUXR1
; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR
; increment DEST address
0010 70F6JNZ LOOP
; check for 0 terminator
0012 05A2 INC AUXR1
; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a par-
ticular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
4233G–8051–03/03
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet T83C5101.PDF ] | |
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