PDF ATA6020N Data sheet ( Hoja de datos )

Número de pieza	ATA6020N
Descripción	Low-current Microcontroller
Fabricantes	ATMEL Corporation
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No Preview Available ! Features/Benefits • Programmable System Clock with Prescaler and Three Different Clock Sources • Very Low Sleep Current (< 1 µA) • Very Low Power Consumption in Active, Power-down and Sleep Mode • 2-Kbyte ROM, 256 × 4-bit RAM • 12 Bi-directional I/Os • Up to 6 External/Internal Interrupt Sources • Synchronous Serial Interface (2-wire, 3-wire) • Multifunction Timer/Counter with – Watchdog, POR and Brown-out Function – Voltage Monitoring Inclusive Lo_BAT Detection – Flash Controller ATAM893 Available (SSO20) – Code-efficient Instruction Set – High-level Language Programming with qFORTH Compiler 1. Description The ATA6020N is a member of Atmel’s 4-bit single-chip microcontroller family. It con- tains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter with modulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external clock input and integrated RC-oscillators. Figure 1-1. Block Diagram VSS VDD OSC1 www.DataSheet4U.com Low-current Microcontroller for Watchdog Function ATA6020N BP20/NTE BP21 BP22 BP23 Brown-out protect RESET Voltage monitor External input VMI RC oscillators External clock input Clock management ROM 2 K x 8 bit RAM 256 x 4 bit MARC4 4-bit CPU core I/O bus Data direction + alternate function Port 4 Data direction + interrupt control Port 5 UTCM Timer 1 interval- and watchdog timer Timer 2 8/12-bit timer with modulator SSI Serial interface T2I T2O SD SC BP40 BP42 INT3 SC T2O BP41 BP43 VMI INT3 T2I SD BP50 BP52 INT6 INT1 BP51 BP53 INT6 INT1 Rev. 4708D–4BMCU–09/05 1 page ATA6020N 4.1.2 RAM The ATA6020N contains 256 x 4-bit wide static random access memory (RAM), which is used for the expression stack. The return stack and data memory are used for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. Figure 4-3. RAM Map FCh RAM (256 x 4-bit) Autosleep X Y SP TOS-1 RP 04h 00h Expression stack FFh Global variables 30 TOS TOS-1 TOS-2 SP 4-bit Expression stack Return stack Global 07h variables 03h Return stack 11 0 RP 12-bit 4.1.2.1 Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arith- metic, I/O and memory reference operations take their operands, and return their results to the expression stack. The MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for passing parameters between subrou- tines and as a scratch pad area for temporary storage of data. 4.1.2.2 Return Stack The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a user definable location and maximum depth. 4.1.3 Registers The MARC4 controller has seven programmable registers and one condition code register. They are shown in the following programming model. 4708D–4BMCU–09/05 5 5 Page ATA6020N 4.2 Master Reset The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, the brown-out detection circuitry, a watchdog time-out, or an external input clock supervisor stage (see Figure 4-7). A master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. During the power-on reset phase, the I/O bus control signals are set to reset mode, thereby, initializing all on-chip peripherals. All bi-directional ports are set to input mode. Attention: During any reset phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. This pin must not be pulled down to VSS during reset by any external circuitry representing a resistor of less than 150 kΩ. Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h. This activates the initialization routine $RESET which in turn has to initialize all necessary RAM variables, stack pointers and peripheral configuration registers. Figure 4-7. Reset Configuration VVDDDD Pull-up NRST CCLL RReesseett rreess ttiimmeerr IInntteerrnnaall rreesseett CCLL==SSYYSSCCLL//44 PPoowweerr--oonn rreesseett BBrroowwnn--oouutt ddeetteeccttiioonn VVDDDD VVSSSS VDDDD VSSSS WWddaaoottcgcghh--rreess CCWWDD EExxtt.. cclloocckk ssuuppeerrvviissoorr EExxIInn 4.2.1 Power-on Reset and Brown-out Detection The ATA6020N has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. These circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. A reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power-down mode is acti- vated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-down mode the brown-out detection is disabled. Two values for the brown-out voltage threshold are programmable via the BOT bit in the SC-register. 4708D–4BMCU–09/05 11 11 Page

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