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부품번호 | ATAM894 기능 |
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기능 | 8k-flash Microcontroller | ||
제조업체 | ATMEL Corporation | ||
로고 | |||
전체 30 페이지수
Features
• 8 K × 8-bit EEPROM
• EEPROM Programmable Options
• Read Protection for the EEPROM Program Memory
• 256 × 4-bit RAM
• 2 × 32 × 16-bit Data EEPROM
• Up to Seven External/Internal Interrupt Sources
• Eight Hardware and Software Interrupt Priorities
• 16 Bi-directional I/Os
• Wide Supply-voltage Range (1.8V to 6.5V)
• Very Low Sleep Current (< 1 µA)
• Synchronous Serial Interface (2-wire, 3-wire)
• Multifunction Timer/Counter with Prescaler/Interval Timer
• Voltage Monitoring Inclusive Lo_BAT Detect
• Watchdog, POR and Brown-out Function
8k-flash
Microcontroller
ATAM894
1. Description
The ATAM894 is a member of the Atmel’s family of 4-bit single chip microcontrollers
with 8K × 8-bit EEPROM program memory. It is based on the 4-K MTP version
ATAM893 and fully compatible with this MTP and the ROM versions ATAR090/890
and ATAR092/892.
Figure 1-1.
Block Diagram
VSS VDD
OSC1 OSC2
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BP10
BP13
BP20/NTE
BP21
BP22
BP23
Brown-out protect.
RESET
Voltage monitor
External input
VMI
Port 1
RC Crystal External
oscillators oscillators clock input
Clock management
EEPROM RAM
8 K x 8 bit 256 x 4 bit
MARC4
4-bit CPU core
I/O bus
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
with prescaler
Modulator 2
SSI
Serial interface
Modulator 3
Demodulator
Timer 3
timer/counter
T2I
T2O
SD
SC
T3O
T3I
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
Data dir. +
alt. function
Port 6
EEPROM
2 x 32 x 16 bit
SD
SC
BP40 BP42
INT3
T2O
SC
BP41
BP43
VMI INT3
T2I SD
BP50
INT6
BP52
INT1
BP51
INT6
BP53
INT1
BP60 BP63
T3O T3I
Rev. 4679D–4BMCU–05/05
4.4 Reset Function
During each reset (power-on or brown-out) the configuration register is reset and reloaded with
the data from the configuration memory. This leads to a slightly different behavior compared to
the ROM versions. Both devices switch their I/Os to input during reset but the ROM part has the
mask selected pull-up or pull-down resistors active while the MTP has them removed until the
download is finished.
5. MARC4 Architecture
5.1 General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip
peripherals. The CPU is based on the Harvard architecture with physically separate program
memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus, are used for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by allowing both instruction prefetching,
and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful
integrated interrupt controller with associated eight prioritized interrupt levels supports fast and
efficient processing of hardware events. The MARC4 is designed for the high-level programming
language qFORTH. The core includes both, an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 5-1. MARC4 Core
Reset
Reset
Clock
System
clock
Sleep
Program
memory
MARC4 CORE
X
Y
PC
SP
RP
RAM
256 x 4-bit
Instruction
bus
Instruction
decoder
Interrupt
controller
I/O bus
Memory bus
CCR
TOS
ALU
On-chip peripheral modules
4 ATAM894
4679D–4BMCU–05/05
4페이지 5.2.3.2
5.2.3.3
5.2.3.4
5.2.3.5
ATAM894
Figure 5-4. Programming Model
11
PC
0
7
RP
7
SP
RBR
3
0
-- --
0
00
0
7
X
7
Y
0
0
TOS
CCR
30
30
C -- B I
Program counter
ROM banking register
Return stack pointer
Expression stack pointer
RAM address register (X)
RAM address register (Y)
Top of stack register
Condition code register
Interrupt enable
Branch
Reserved
Carry/borrow
ROM Banking Register (RBR)
The ROM banking register is a 4-bit register whereby the ATAM894 only uses 2 bit. This register
indicates which ROM bank is presently being addressed. The RBR is accessed with a standard
qFORTH peripheral read or write instruction (IN or OUT, port address 'D' hex).
RAM Address Registers
The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These
registers allow access to any of the 256 RAM nibbles.
Expression Stack Pointer (SP)
The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression
stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-
decremented if a nibble is removed from the stack. Every post-decrement operation moves the
item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack pointer
has to be initialized with “>SP S0” to allocate the start address of the expression stack area.
Return Stack Pointer (RP)
The return stack pointer points to the top element of the 12-bit wide return stack. The pointer
automatically pre-increments if an element is moved onto the stack, or it post-decrements if an
element is removed from the stack. The return stack pointer increments and decrements in
steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left
unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset
the return stack pointer has to be initialized via “>RP FCh”.
4679D–4BMCU–05/05
7
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부품번호 | 상세설명 및 기능 | 제조사 |
ATAM894 | 8k-flash Microcontroller | ATMEL Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |