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PDF ATAR092-D Data sheet ( Hoja de datos )
| Número de pieza | ATAR092-D | |
| Descripción | Low-current Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Extended Temperature Range for High Temperature up to 125°C
• 4-Kbyte ROM, 256 × 4-bit RAM
• 16 Bi-directional I/Os
• Up to 7 External/Internal Interrupt Sources
• Multifunction Timer/Counter with
– IR Remote Control Carrier Generator
– Bi-phase, Manchester and Pulse-width Modulator and Demodulator
– Phase Control Function
• Programmable System Clock with Prescaler and Five Different Clock
Sources
• Wide Supply-voltage Range (1.8 V to 6.5 V)
• Very Low Sleep Current (< 1 µA)
• Synchronous Serial Interface (2-wire, 3-wire)
• Watchdog, POR and Brown-out Function
• Voltage Monitoring Inclusive Lo_BAT Detect
• Flash Controller ATAM893 Available (SSO20)
Description
The ATAR092-D is a member of Atmel’s family of 4-bit single-chip microcontrollers. It
offers the highest integration for IR and RF data communication, remote-control and
phase-control applications. The ATAR092-D is suitable as a transmitter as well as a
receiver. They contain ROM, RAM, parallel I/O ports, two 8-bit programmable multi-
function timer/counters with modulator and demodulator function, voltage supervisor,
interval timer with watchdog function and a sophisticated on-chip clock generation
w i t h ex t e r n a l c l o ck i n p u t , i n t e g ra t e d R C - , 3 2 -k H z c r y s t a l - a n d 4 - M H z
crystal-oscillators.
www.DataSheet4U.com
Figure 1. Block Diagram
VSS VDD
OSC1 OSC2
Low-current
Microcontroller
for Wireless
Communication
ATAR092-D
BP10
BP13
BP20/NTE
BP21
BP22
BP23
Brown-out protect.
RESET
Voltage monitor
External input
VMI
Port 1
RC
Crystal
External
oscillators oscillators clock input
Clock management
ROM
4 K x 8 bit
RAM
256 x 4 bit
MARC4
4-bit CPU core
I/O bus
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
8/12-bit timer
with modulator
SSI
Serial interface
T2I
T2O
SD
SC
Timer 3
T3O
8-bit
timer/counter
with modulator
and demodulator
T3I
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
Data direction +
alternate function
Port 6
BP40 BP42
INT3 T2O
SC
BP41 BP43
VMI INT3
T2I SD
BP50
INT6
BP52
INT1
BP51
INT6
BP53
INT1
BP60
T3O
BP63
T3I
Rev. 4594C–4BMCU–12/04
1 page  
Registers
Program Counter (PC)
4594C–4BMCU–12/04
ATAR092-D
Figure 5. RAM Map
RAM
(256 x 4-bit)
Autosleep
FCh
X
Y
SP TOS-1
RP
04h
00h
Expression stack
FFh
Global
variables
30
TOS
TOS-1
TOS-2
SP
4-bit
Expression
stack
Return
stack
Global
07h variables
03h
Return stack
11 0
RP
12-bit
The MARC4 controller has seven programmable registers and one condition code regis-
ter. They are shown in the following programming model (Figure 6).
The program counter is a 12-bit register which contains the address of the next instruc-
tion to be fetched from ROM. Instructions currently being executed are decoded in the
instruction decoder to determine the internal micro-operations. For linear code (no calls
or branches) the program counter is incremented with every instruction cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address. The program counter is also used with the table instruction
to fetch 8-bit wide ROM constants.
Figure 6. Programming Model
11
PC
7
RP
7
SP
7
X
7
Y
0
0
00
0
0
0
TOS
CCR
30
30
C -- B I
Program counter
Return stack pointer
Expression stack pointer
RAM address register (X)
RAM address register (Y)
Top of stack register
Condition code register
Interrupt enable
Branch
Reserved
Carry/borrow
5
5 Page 
ATAR092-D
Figure 10. Brown-out Detection
VDD
2.0 V
1.7 V
CPU
Reset BOT = 1
CPU
Reset BOT = 0
td
td
td = 1.5 ms (typically)
BOT = 1, low brown-out voltage threshold 1.7 V (is reset value).
BOT = 0, high brown-out voltage threshold 2.0 V.
td
t
Watchdog Reset
External Clock Supervisor
Voltage Monitor
The watchdog’s function can be enabled at the WDC register and triggers a reset with
every watchdog counter overflow. To suppress the watchdog reset, the watchdog
counter must be regularly reset by reading the watchdog register address (CWD). The
CPU reacts in exactly the same manner as a reset stimulus from any of the above
sources.
The external input clock supervisor function can be enabled if the external input clock is
selected within the CM and SC registers of the clock module. The CPU reacts in exactly
the same manner as a reset stimulus from any of the above sources.
The voltage monitor consists of a comparator with internal voltage reference. It is used
to supervise the supply voltage or an external voltage at the VMI pin. The comparator for
the supply voltage has three internal programmable thresholds one lower threshold
(2.2 V), one middle threshold (2.6 V). and one higher threshold (3.0 V). For external
voltages at the VMI pin, the comparator threshold is set to VBG = 1.3 V. The VMS bit
indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this thresh-
old. An interrupt can be generated when the VMS bit is set or reset to detect a rising or
falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit
(VIM) is reset in the VMC register.
4594C–4BMCU–12/04
11
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