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PDF SY100S301 Data sheet ( Hoja de datos )
| Número de pieza | SY100S301 | |
| Descripción | Triple 5-INPUT Or/nOR GATE | |
| Fabricantes | Micrel Semiconductor | |
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TRIPLE 5-INPUT
OR/NOR GATE
SY100S301
FINAL
FEATURES
DESCRIPTION
s Max. propagation delay of 750ps
s IEE min. of –25mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for
improved noise immunity
s 20% faster than Fairchild 300K at lower power
s Internal 75KΩ input pull-down resistors
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
The SY100S301 is an ultra-fast triple 5-input OR/NOR
gate designed for use in high-performance ECL systems.
The inputs on this device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
D5a
D1b
VEE
VEES
D2b
D3b
D4b
11 10 9 8 7 6 5
12 4
13 3
14 Top View
2
15
PLCC
J28-1
1
16 28
17 27
18 26
19 20 21 22 23 24 25
Ob
Ob
VCCA
VCC
VCC
Oc
Oc
D1a
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D2a Oa
D3a
D4a Oa
D5a
D1b
D2b Ob
D3b
D4b Ob
24 23 22 21 20 19
D5b 1
18 D4a
D1c 2
17 D3a
D2c 3
D3c 4
D4c 5
Top View
Flatpack
F24-1
16
15
14
D2a
D1a
Oa
D5c 6
13 Oa
7 8 9 10 11 12
D5b
D1c
D2c Oc PIN NAMES
D3c
D4c
Oc
Pin Function
D5c
Dna, Dnb, Dnc
Data Inputs (n-1...5)
Oa, Ob, Oc
Data Outputs
Oa, Ob, Oc
Complementary Data Outputs
VEES
VEE Substrate
VCCA
VCCO for ECL Outputs
Rev.: F
Amendment: /0
1 Issue Date: July, 1999
1 page  
Micrel
28 LEAD PLCC (J28-1)
SY100S301
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet SY100S301.PDF ] | |
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