PDF SY100S336A Data sheet ( Hoja de datos )

Número de pieza	SY100S336A
Descripción	Enhanced 4-STAGE Counter/shift Register
Fabricantes	Micrel Semiconductor
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No Preview Available ! ENHANCED 4-STAGE COUNTER/SHIFT REGISTER SY100S336A FINAL FEATURES DESCRIPTION s Max. shift frequency of 700MHz The SY100S336A is functionally the same as the s Clock to Q delay max. of 1100ps s Sn to TC speed improved by 50% s Sn set-up and hold time reduced by more than 50% s IEE min. of –170mA SY100S336, but has Sn to TC speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter. The SY100S336A functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is s Industry standard 100K ECL levels s Internal 75KΩ input pull-down resistors s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved designed for use in high-performance ECL systems. Three Select inputs (Sn) are provided for determining the mode of operation. The Function Table lists the available modes of operation. In order to allow cascading for multistage counters, two Count Enable controls (CEP, CET) are provided. The CET input also functions as the Serial Data noise immunity input (S0) for a shift-up operation, while the D3 input serves s 50% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages as the Serial Data input for the shift-down operation. When the device is in the counting mode, the Terminal Count (TC) goes to a logical LOW when the count reaches 15 for count-up or reaches 0 for count-down. When in the shift mode, the TC output simply repeats the Q3 output. The flexiblity provided by the TC/Q3 output and the D0/ CET input allows these signals to be interconnected from PIN CONFIGURATIONS one stage to the next higher stage for multistage counting or shift-up operations. The individual Presets (Pn) allow www.DataSheet4U.com initialization of the counter by entering data in parallel to preset the counter. A logic HIGH on the Master Reset (MR) overrides all other inputs and asynchronously clears the 11 10 9 8 7 6 5 flip-flops. An additional synchronous Clear is provided, as P0 12 4 Q2 well as a complement function which synchronously inverts CP VEE VEES MR S0 13 14 15 16 17 Top View PLCC J28-1 3 Q2 2 VCCA 1 VCC 28 VCC 27 Q1 the contents of the flip-flops. All inputs have 75KΩ pull- down resistors. PIN NAMES S1 18 26 Q1 19 20 21 22 23 24 25 Pin Function CP Clock Pulse Input CEP Count Enable Parallel Input (Active LOW) S2 CEP D0/CET TC Q0 Q0 24 23 22 21 20 19 1 18 2 17 3 Top View 16 4 Flatpack F24-1 15 5 14 6 13 7 8 9 10 11 12 P1 P2 P3 D3 Q3 Q3 D0/CET S0 — S2 MR VEES VCCA P0 – P3 Serial Data Input/Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input VEE Substrate VCCO for ECL Outputs Preset Inputs D3 Serial Data Input TC Terminal Count Output Q0 — Q3 Data Outputs Q0 — Q3 Complementary Data Outputs Rev.: G Amendment: /0 1 Issue Date: July, 1999 1 page Micrel AC ELECTRICAL CHARACTERISTICS PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND Symbol Parameter TA = 0°C Min. Max. TA = +25°C Min. Max. fshift Shift Frequency 700 — 700 — tPLH Propagation Delay tPHL CP to Qn, Qn 450 1100 450 1100 tPLH Propagation Delay tPHL CP to TC 600 1800 600 1800 tPLH Propagation Delay tPHL MR to Qn, Qn 500 1300 500 1300 tPLH Propagation Delay tPHL MR to TC 600 1800 600 1800 tPLH Propagation Delay tPHL D0/CET to TC 400 1100 400 1100 tPLH Propagation Delay tPHL Sn to TC 400 1500 400 1500 tTLH Transition Time300 tTHL 20% to 80%, 80% to 20% 900 300 900 300 tS Set-up Time D3 Pn D0/CET to CEP Sn MR (Release Time) 800 800 700 1000 900 — 800 — — 800 — — 700 — — 1000 — — 900 — tH Hold Time D3 Pn D0/CET to CEP Sn 200 — 200 — 200 — 200 — 200 — 200 — -200 — -200 — tpw (H) Pulse Width HIGH, CP, MR — 800 — 800 TA = +85°C Min. Max. 700 — 450 1100 600 1800 500 1300 600 1800 400 1100 400 1500 900 ps 800 800 700 1000 900 — — — — — 200 200 200 -200 — — — — — 800 Unit MHz ps ps ps ps ps ps ps ps ps SY100S336A Condition 5 5 Page

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