PDF SY100S336 Data sheet ( Hoja de datos )

Número de pieza	SY100S336
Descripción	4-STAGE Counter/shift Register
Fabricantes	Micrel Semiconductor
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No Preview Available ! 4-STAGE COUNTER/ SHIFT REGISTER SY100S336 FINAL FEATURES DESCRIPTION s Max. shift frequency of 700MHz The SY100S336 functions either as a modulo-16 up/ s Clock to Q delay max. of 1100ps s IEE min. of –170mA s Internal 75KΩ input pull-down resistors down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three Select inputs (Sn) are provided for determining the mode of operation. The Function Table lists the available modes of s Industry standard 100K ECL levels operation. In order to allow cascading for multistage s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s 50% faster than Fairchild 300K at lower power counters, two Count Enable controls (CEP, CET) are provided. The CET input also functions as the Serial Data input (S0) for a shift-up operation, while the D3 input serves as the Serial Data input for the shift-down operation. When the device is in the counting mode, the Terminal Count (TC) goes to a logical LOW when the count reaches s Function and pinout compatible with Fairchild F100K 15 for count-up or reaches 0 for count-down. When in the s Available in 24-pin CERPACK and 28-pin PLCC packages shift mode, the TC output simply repeats the Q3 output. The flexiblity provided by the TC/Q3 output and the D0/ CET input allows these signals to be interconnected from one stage to the next higher stage for multistage counting or shift-up operations. The individual Presets (Pn) allow PIN CONFIGURATIONS initialization of the counter by entering data in parallel to preset the counter. A logic HIGH on the Master Reset (MR) overrides all other inputs and asynchronously clears the flip-flops. An additional synchronous Clear is provided, as www.DataSheet4U.com well as a complement function which synchronously inverts 11 10 9 8 7 6 5 the contents of the flip-flops. All inputs have 75KΩ pull- down resistors. P0 12 4 Q2 CP 13 3 Q2 VEE VEES MR S0 14 15 16 17 Top View PLCC J28-1 2 VCCA 1 VCC 28 VCC 27 Q1 PIN NAMES Pin Function S1 18 26 Q1 CP Clock Pulse Input 19 20 21 22 23 24 25 CEP Count Enable Parallel Input (Active LOW) D0/CET Serial Data Input/Count Enable Trickle Input (Active LOW) S2 CEP D0/CET TC Q0 Q0 24 23 22 21 20 19 1 18 2 17 3 Top View 16 4 Flatpack F24-1 15 5 14 6 13 7 8 9 10 11 12 P1 P2 P3 D3 Q3 Q3 S0 — S2 MR VEES VCCA P0 – P3 D3 TC Select Inputs Master Reset Input VEE Substrate VCCO for ECL Outputs Preset Inputs Serial Data Input Terminal Count Output Q0 — Q3 Data Outputs Q0 — Q3 Complementary Data Outputs Rev.: G Amendment: /0 1 Issue Date: July, 1999 1 page Micrel AC ELECTRICAL CHARACTERISTICS PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C TA = +25°C Symbol Parameter Min. Max. Min. Max. fshift Shift Frequency700 tPLH Propagation Delay tPHL CP to Qn, Qn — 700 — 700 450 1100 450 1100 tPLH Propagation Delay tPHL CP to TC 600 1800 600 1800 tPLH Propagation Delay tPHL MR to Qn, Qn tPLH Propagation Delay tPHL MR to TC 500 1300 500 1300 600 1800 600 1800 tPLH Propagation Delay tPHL D0/CET to TC 400 1100 400 1100 tPLH Propagation Delay tPHL Sn to TC 1500 2500 1500 2500 tTLH Transition Time tTHL 20% to 80%, 80% to 20% 300 900 300 900 tS Set-up Time D3 Pn D0/CET to CEP Sn MR (Release Time) 800 800 700 2000 900 — 800 — — 800 — — 700 — — 2000 — — 900 — tH Hold Time D3 Pn D0/CET to CEP Sn 200 — 200 — 200 — 200 — 200 — 200 — -600 — -600 — tpw (H) Pulse Width HIGH, CP, MR — 800 — 800 TA = +85°C Min. Max. — MHz 450 1100 600 1800 500 1300 600 1800 400 1100 1500 2500 300 900 800 800 700 2000 900 — — — — — 200 200 200 -600 — — — — — 800 Unit ps ps ps ps ps ps ps ps ps ps SY100S336 Condition 5 5 Page

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