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PDF SY100S331 Data sheet ( Hoja de datos )
| Número de pieza | SY100S331 | |
| Descripción | Triple D Flip-flop | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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TRIPLE D
FLIP-FLOP
SY100S331
FINAL
FEATURES
DESCRIPTION
s Max. toggle frequency of 800MHz
s Differential outputs
s IEE min. of –80mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 150% faster than Fairchild
s 40% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CPc), as well as
its own clock pulse (CPn). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CPc
and CPn are LOW and enters the slave on the rising edge
of either CPc or CPn (or both).
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SDn) and Direct Clear (CDn) signals. The MR,
MS, SDn and DCn signals override the clock signals. The
inputs on this device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
BLOCK DIAGRAM
CD2
CPC
CP2
D2
SD2
CD1
CP1
D1
SD1
CD0
CP0
D0
SD0
CD
CP
D SD
CD
CP
D SD
CD
CP
D SD
www.DataSheet4U.com
MS
11 10 9 8 7 6 5
12 4
Q1
CPC 13
3 Q1
VEE 14
Top View
2 VCCA
Q2
VEES
15
PLCC
1 VCC
MR 16
J28-1
28 VCC
Q2
SD1 17
27 Q2
D1 18
26 Q2
19 20 21 22 23 24 25
Q1
Q1 24 23 22 21 20 19
CP1 1
18 SD0
CD1 2
17 CD0
SD2 3
Top View 16 CP0
Q0
CD2 4
Flatpack
F24-1
15
D0
CP2 5
14 Q0
Q0
D2 6
13 Q0
7 8 9 10 11 12
MS MR
Rev.: G Amendment: /0
1 Issue Date: July, 1999
1 page  
Micrel
TIMING DIAGRAMS
DATA
CLOCK
tS
50%
th
50%
+1.05V
+0.31V
+1.05V
+0.31V
Data Setup and Hold Time
NOTES:
ts is the minimum time before the transition of the clock that information must be present at the data input.
th is the minimum time after the transition of the clock that information must remain unchanged at the data input.
SY100S331
PRODUCT ORDERING CODE
Ordering
Code
SY100S331FC
SY100S331JC
SY100S331JCTR
Package
Type
F24-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SY100S331.PDF ] | |
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