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PDF SY100S355 Data sheet ( Hoja de datos )
| Número de pieza | SY100S355 | |
| Descripción | Quad Multiplexer/latch | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY100S355 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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QUAD
MULTIPLEXER/LATCH
SY100S355
FINAL
FEATURES
DESCRIPTION
s Max. propagation delay of 1100ps
s Max. enable to output delay of 1400ps
s IEE min. of –80mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 50% faster than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S355 offers four transparent latches with
differential outputs and is designed for use in high-
performance ECL systems. The Select inputs (S0, S1)
select one of the two sources of input data (D0 or D1) to the
latch. The Select inputs can also force the outputs to a logic
LOW when the latch is in the transparent mode. The
latches are in the transparent mode when both Enables
(E1, E2) are at a logic LOW state. In the transparent mode,
the Select inputs can pass an input logic HIGH from D0 or
D1 to the output.
If the Select inputs are tied together, then input data from
either D0 or D1 is always passed through. A rising edge on
either Enable input will latch the outputs with the most
recent data at the latch inputs being stored. The Master
Reset (MR) input overrides all other inputs and takes the Q
outputs to a logic LOW. The inputs on this device have
75KΩ pull-down resistors.
BLOCK DIAGRAM
S0
S1
D0a
D1a
D0b
D1b
D0c
D1c
D0d
D1d
E1
E2
MR
PIN CONFIGURATIONS
DQ
E
CD
DQ
E
CD
DQ
E
CD
DQ
E
CD
www.DataSheet4U.com
S0
Qa S1
VEE
Qa VEES
MR
E1
E2
Qb
11 10 9 8 7 6 5
12
13
14 Top View
15 PLCC
16 J28-1
17
18
4
3
2
1
28
27
26
19 20 21 22 23 24 25
Qb
Qb
VCCA
VCC
VCC
Qc
Qc
Qb
24 23 22 21 20 19
D0c 1
18 D1b
D1c 2
17 D0b
Qc
D0d 3
Top View 16 D1a
D1d 4
Flatpack
F24-1
15
D0a
Qc
Qd 5
14 Qa
Qd 6
13 Qa
7 8 9 10 11 12
Qd
Qd
Rev.: G Amendment: /0
1 Issue Date: July, 1999
1 page  
Micrel
TIMING DIAGRAMS
S0, S1
DATA
E1, E2
50%
tS tH
50%
tS tH
50%
–0.95V
–1.69V
–0.95V
–1.69
–0.95V
–1.69V
Data Set-up and Hold Times
NOTES:
1. VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
2. ts is the minimum time before the transition of the clock that information
must be present at the data input.
3. tH is the minimum time after the transition of the clock that information must
remain unchanged at the data input.
SY100S355
PRODUCT ORDERING CODE
Ordering
Code
SY100S355FC
SY100S355JC
SY100S355JCTR
Package
Type
F24-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SY100S355.PDF ] | |
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