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PDF SY100S350 Data sheet ( Hoja de datos )
| Número de pieza | SY100S350 | |
| Descripción | Hex D-latch | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY100S350 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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HEX D-LATCH
SY100S350
FINAL
FEATURES
DESCRIPTION
s Max. transparent propagation delay of 900ps
s Min. Master Reset and Enable pulse widths of 100ps
s IEE min. of –98mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s More than 40% faster than Fairchild
s Approximately 30% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S350 offers six high-speed D-Latches with
both true and complement outputs, and is performance
compatible for use with high-performance ECL systems.
When both enable signals (Ea and Eb) are at a logic LOW,
the latches are transparent and the input signals( D0–D5)
appear at the outputs (Q0–Q5) after a propagation delay. If
either or both of the enable signals are at a logic HIGH, then
the latches store the last valid data present on its inputs
before Ea or Eb went to a logic HIGH. The Master Reset
(MR) overrides all other input signals and takes the outputs
to a logic LOW state. All inputs have 75KΩ pull-down
resistors.
PIN CONFIGURATIONS
BLOCK DIAGRAM
D5 D
Eb
Ea
ER
MR
D4 D
ER
D3 D
ER
D2 D
ER
D1 D
ER
D0 D
ER
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
D2
D3
VEE
www.DataSheet4VUE.cEomS
MR
Ea
Eb
11 10 9 8 7 6 5
12 4
13 3
14 Top View
15 PLCC
16 J28-1
2
1
28
17 27
18 26
19 20 21 22 23 24 25
Q2
Q2
VCCA
VCC
VCC
Q3
Q3
24 23 22 21 20 19
D4 1
18
D5 2
17
Q5 3
Q5 4
Q4 5
Top View
Flatpack
F24-1
16
15
14
Q4 6
13
7 8 9 10 11 12
D1
D0
Q0
Q0
Q1
Q1
Rev.: G Amendment: /0
1 Issue Date: July, 1999
1 page  
Micrel
TIMING DIAGRAMS
DATA
ENABLE
tS th
Data Set-up and Hold Times
NOTES:
tS is the minimum time before the transition of the clock that information must be present at the data input.
tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.
SY100S350
PRODUCT ORDERING CODE
Ordering
Code
SY100S350FC
SY100S350JC
SY100S350JCTR
Package
Type
F24-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SY100S350.PDF ] | |
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