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PDF SY100S341 Data sheet ( Hoja de datos )
| Número de pieza | SY100S341 | |
| Descripción | 8-BIT Shift Register | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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8-BIT SHIFT
REGISTER
SY100S341
FINAL
FEATURES
DESCRIPTION
s Max. shift frequency of 600MHz
s Max. Clock to Q delay of 1200ps
s IEE min. of –150mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 70% faster than Fairchild 300K at lower power
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S341 offer eight D-type, edge-triggered flip-
flops with both individual inputs for parallel operation as
well as serial inputs for bidirectional shifting, and are
designed for use in high-performance ECL systems. Data
is clocked into the flip-flops on the rising edge of the clock.
The mode of operation is selected by two Select inputs
(S0, S1) which determine if the device performs a shift, hold
or parallel entry function, as described in the Truth Table.
The inputs on these devices have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
PIN NAMES
Label
CP
S0 — S1
D0 — D7
P0 — P7
Q0 — Q7
VEES
VCCA
Function
Clock Pulse Input
Select Inputs
Serial Inputs
Parallel Inputs
Data Outputs
VEE Substrate
VCCO for ECL Outputs
P4
CP
VEE
VEES
S0
www.DataSheet4U.cSom1
P3
11 10 9 8 7 6 5
12
13
14 Top View
15 PLCC
16 J28-1
17
18
4
3
2
1
28
27
26
19 20 21 22 23 24 25
Q5
Q4
VCCA
VCC
VCC
Q3
Q2
24 23 22 21 20 19
P2 1
18 P5
P1 2
17 P6
P0 3
D0 4
Q0 5
Top View
Flatpack
F24-1
16
15
14
P7
D7
Q7
Q1 6
13 Q8
7 8 9 10 11 12
Rev.: G
Amendment: /0
1 Issue Date: July, 1999
1 page  
Micrel
TIMING DIAGRAMS
Pn, Sn, Dn
CLOCK
tS
50%
tH
50%
–0.95V
–1.69V
–0.95V
–1.69V
Set-up and Hold Times
NOTES:
1. VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND.
2. tS is the minimum time before the transition of the clock that information must be present at the data input.
3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.
SY100S341
PRODUCT ORDERING CODE
Ordering
Code
SY100S341FC
SY100S341JC
SY100S341JCTR
Package
Type
F24-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SY100S341.PDF ] | |
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