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PDF SY100S891 Data sheet ( Hoja de datos )
| Número de pieza | SY100S891 | |
| Descripción | 5-BIT Registered Transceiver | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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5-BIT REGISTERED
TRANSCEIVER
SY100S891
FINAL
FEATURES
DESCRIPTION
s 25Ω cut-off bus outputs
s 50Ω receiver outputs
s Transmit and receive registers with separate clocks
s 1500ps max. delay from CLK1 to Bus Outputs (BUS)
s 1500ps max. delay from CLK2 to Receiver Outputs (Q)
s Individual bus enable pins
s Internal 75KΩ input pull-down resistors
s Voltage and temperature compensation for improved
noise immunity
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Available in 28-pin PLCC package
The SY100S891 is a 5-bit registered transceiver
containing five bus transceivers with both transmit and
receive registers. The bus outputs (BUS0 – BUS4) are
specified for driving a 25 ohm bus and the receive outputs
(Q0 – Q4) are specified for driving a 50 ohm line. The
bus outputs have a normal high level output voltage and
a normal low level output voltage when the bus enable
(BUSEN0 – BUSEN4) is high. However, the output is
switched to a cut-off level when a bus-enable is low.
This cut-off level is sufficiently low that a relatively high
impedance is presented to the bus in order to minimize
reflections. There is one bus-enable for each bus driver;
a clock (CLK1) which is common to all five bus driver
registers; and a separate clock (CLK2) which is common
to all five receive registers. Data at the D inputs is clocked
to the Bus register by a positive transition of CLK1 and
data on the bus is clocked into the Receiver register by
a positive transition of CLK2. A high on the Master Reset
clears all registers.
PIN CONFIGURATION
PIN NAMESwww.DataSheet4U.com
MR
CLK2
CLK1
VEE
D2
BUSEN2
D1
25 24 23 22 21 20 19
26 18
27 17
28 TOP VIEW 16
1 PLCC 15
J28-1
2 14
3 13
4 12
5 6 7 8 9 10 11
Q3
BUS3
VCC
Q2
BUS2
VCCA
Q1
Pin
BUSEN0–4
D0 – D4
CLK1
CLK2
MR
Q0 – Q4
BUS0–4
Function
Bus Enable Inputs
Data Inputs
Bus Driver Clock Input
Receive Register Clock
Master Reset
Bus Receive Outputs
Bus Outputs
Rev.: E Amendment: /0
1 Issue Date: August, 1998
1 page  
Micrel
28 LEAD PLCC (J28-1)
SY100S891
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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