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부품번호 | SY100S838 기능 |
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기능 | Pecl Clock Generation | ||
제조업체 | Micrel Semiconductor | ||
로고 | |||
전체 4 페이지수
(÷1, ÷2/3) OR (÷2, ÷4/6)
CLOCK GENERATION CHIP
ClockWorks™
SY100S838
SY100S838L
FINAL
FEATURES
DESCRIPTION
s 3.3V and 5V power supply options
The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/
s 50ps output-to-output skew
s Synchronous enable/disable
s Master Reset for synchronization
6) clock generation chip designed explicitly for low skew
clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
s Internal 75KΩ input pull-down resistors
by either a differential or single-ended ECL or, if positive
s Available in 20-pin SOIC package
power supplies are used, PECL input signal. In addition,
by using the VBB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
PIN CONFIGURATION
used, the VBB output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor.
VCC Q0
Q0
Q1
Q1 Q2 Q2
Q3
20 19 18 17 16 15 14 13
Q3 VEE
12 11
The VBB output is designed to act as the switching
reference for the input of the SY100S838/L under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine
TOP VIEW
SOIC
Z20-1
what clock generation chip function is. When FSEL input
is LOW, SY100S838/L functions as a divide by 2 and by
4/6 clock generation chip. However, if FSEL input is HIGH,
it functions as a divide by 1 and by 2/3 clock chip.
The common enable (EN) is synchronous so that the
1
2
3
4
56
7
8
9
10
internal dividers will only be enabled/disabled when the
www.DataSheet4U.com
VCC EN DIVSEL CLK CLK VBB MR VCC NC FSEL
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
TRUTH TABLE
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
CLK EN MR
Function
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
Z L L Divide
synchronization of the internal dividers, as well as for
ZZ H L Hold Q0–3 multiple SY100S838/Ls in a system.
X X H Reset Q0–3
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
PIN NAMES
Pin
Function
FSEL
L
L
H
H
DIVSEL
L
H
L
H
Q0, Q1 OUTPUTS
Divide by 2
Divide by 2
Divide by 1
Divide by 1
Q2, Q3 OUTPUTS
Divide by 4
Divide by 6
Divide by 2
Divide by 3
CLK
FSEL
EN
MR
VBB
Q0, Q1
Differential Clock Inputs
Function Select Input
Synchronous Enable
Master Reset
Reference Output
Differential ÷1 or ÷2 Outputs
Q2, Q3
Differential ÷2/3 or ÷4/6 Outputs
DIVSEL
Frequency Select Input
Rev.: E Amendment: /1
1 Issue Date: August, 1998
Micrel
20 LEAD SOIC .300" WIDE (Z20-1)
ClockWorks™
SY100S838
SY100S838L
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4
4페이지 | |||
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다운로드 | [ SY100S838.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
SY100S834 | Clock Generation Chip | Micrel Semiconductor |
SY100S834 | Pecl Clock Generation | Micrel Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |