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PDF SY100S815 Data sheet ( Hoja de datos )
| Número de pieza | SY100S815 | |
| Descripción | 1:4 Pecl Clock Driver With Selectable TTL or Pecl Clock Input | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SINGLE SUPPLY QUAD
PECL/TTL-TO-PECL
ClockWorks™
SY100S815
FINAL
FEATURES
DESCRIPTION
s Quad PECL version of popular ECLinPS E111
The SY100S815 is a low skew 1-to-4 PECL differential
s Low skew
s Guaranteed skew spec
s TTL enable input
driver designed for clock distribution in new, high-
performance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin TEN.
When the TTL enable pin is HIGH, the TTL input is enabled
s Selectable TTL or PECL clock input
and the PECL input is disabled. When the enable pin is set
s Single +5V supply
s Differential internal design
s PECL I/O fully compatible with industry standard
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
s Internal 75kΩ PECL input pull-down resistors
carefully optimized for minimal gate-to-gate skew within
s Available in 16-pin SOIC package
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S815 shares a common set of “basic”
BLOCK DIAGRAM
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
Q0 propagation delay.
To ensure that the skew specification is met, it is
Q0 necessary that both sides of the differential output are
Q1 terminated into 50Ω, even if only one side is being used. In
EIN
0
EIN
mostQwww1.DataSheet4U.com applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
Q2 nine pairs are used, it is necessary to terminate at least the
TIN 1
Q2 output pairs on the same package side (i.e. sharing the
same VCCO as the pair(s) being used on that side) in order
Q3 to maintain minimum skew.
Q3
TEN
PIN NAMES
Pin
EIN, EIN
TIN
TEN
Q0, Q0 – Q3, Q3
VCC
VEE
Function
Differential PECL Input Pair
TTL Input
TTL Input Enable
Differential PECL Outputs
PECL VCC (+5.0V)
PECL Ground (0V)
PIN CONFIGURATION
VCC 1
EIN 2
TIN 3
Q3 4
Q3 5
Q2 6
Q2 7
VCCO 8
TOP VIEW
SOIC
Z16-1
16 EIN
15 TEN
14 VEE
13 Q0
12 Q0
11 Q1
10 Q1
9 VCCO
Rev.: F Amendment: /0
1 Issue Date: October, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100S815.PDF ] | |
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