PDF SY100S811 Data sheet ( Hoja de datos )

Número de pieza	SY100S811
Descripción	1:9 Pecl Clock Driver With Selectable TTL or Pecl Clock Input
Fabricantes	Micrel Semiconductor
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No Preview Available ! SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL ClockWorks™ SY100S811 FINAL FEATURES DESCRIPTION s PECL version of popular ECLinPS E111 The SY100S811 is a low skew 1-to-9 PECL differential s Low skew s Guaranteed skew spec s VBB output driver designed for clock distribution in new, high- performance PECL systems. It accepts either a PECL clock input or a TTL input by using the TTL enable pin TEN. When the TTL enable pin is HIGH, the TTL input is enabled s TTL enable input and the PECL input is disabled. When the enable pin is set s Selectable TTL or PECL clock input s Single +5V supply s Differential internal design LOW, the TTL input is disabled and the PECL input is enabled. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are s Similar pin configuration to E111 carefully optimized for minimal gate-to-gate skew within s PECL I/O fully compatible with industry standard s Internal 75KΩ PECL input pull-down resistors s Available in 28-pin PLCC and SOIC packages the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the S811 shares a common set of “basic” processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, including BLOCK DIAGRAM propagation delay. To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. ln mostQ0 www.DataSheet4U.com applications, all nine differential pairs will be used Q0 and, therefore, terminated. In the case where fewer than EIN EIN 0 Q1 nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the Q1 same VCCO as the pair(s) being used on that side) in order Q2 to maintain minimum skew. TIN 1 Q2 The VBB output is intended for use as a reference voltage for single-ended reception of PECL signals to that Q3 device only. When using VBB for this purpose, it is Q3 recommended that VBB is decoupled to VCC via a 0.01µF Q4 capacitor. Q4 PIN CONFIGURATION TEN Q5 Q5 Q6 VBB Q6 25 24 23 22 21 20 19 Q7 VEE 26 18 Q3 Q7 TEN 27 17 Q3 Q8 EIN VCC 28 1 TOP VIEW PLCC 16 Q4 15 VCCO Q8 EIN 2 J28-1 14 Q4 VBB 3 13 Q5 TIN 4 12 Q5 5 6 7 8 9 10 11 Rev.: F Amendment: /0 1 Issue Date: October, 1998 1 page Micrel 28 LEAD SOIC .300" WIDE (Z28-1) Rev. 02 MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 5 5 Page

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