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PDF SY100S391 Data sheet ( Hoja de datos )
| Número de pieza | SY100S391 | |
| Descripción | Low-power Hex Ttl-to-pecl Translator | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY100S391 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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LOW-POWER
HEX TTL-TO-PECL
TRANSLATOR
SY100S391
FINAL
FEATURES
DESCRIPTION
s Operates from a single +5V supply
s Differential PECL outputs
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
E
D0
Q0
Q0
The SY100S391 is a hex TTL-to-PECL translator for
converting TTL logic levels to 100K logic levels. The unique
feature of this translator is the ability to do this translation
using only one +5V supply. The differential outputs allow
each circuit to be used as an inverting/non-inverting translator,
or as a differential line driver. A common enable (E), when
LOW, holds all inverting outputs HIGH and all non-inverting
inputs LOW.
The SY100S391 is ideal for those mixed PECL/TTL
applications which only have a +5V supply available. When
used in the differential mode, the S391, due to its high
common mode rejection, overcomes voltage gradients
between the TTL and PECL ground systems.
PIN CONFIGURATIONS
Q1
D1 Q1
11 10 9 8 7 6 5
D2 12
4 Q2
Q2
www.DataSheet4UG.cNomD TTL
13
3 Q2
D2
Q2
GND PECL 14
Top View
2 VCCA
GNDS 15
PLCC
1 VCC
D3
Q3
GND PECL
E
16
17
J28-1
28 VCC
27 Q3
Q3
D3 18
26 Q3
Q4
D4 Q4
19 20 21 22 23 24 25
Q5
D5 Q5
PIN NAMES
Pin
D0 — D5
Q0 — Q5
Q0 — Q5
E
VCCA
Function
Data Inputs (TTL)
Data Outputs (PECL)
Inverting Data Outputs (PECL)
Enable Input (TTL)
VCCO for ECL Outputs
24 23 22 21 20 19
D4 1
18 D1
D5 2
17 D0
Q5 3
Q5 4
Q4 5
Top View 16 Q0
Flatpack
F24-1
15
Q0
14 Q1
Q4 6
13 Q1
7 8 9 10 11 12
Rev.: G Amendment: /0
1 Issue Date: July, 1999
1 page  
Micrel
24 LEAD CERPACK (F24-1)
SY100S391
Rev. 03
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet SY100S391.PDF ] | |
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