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PDF SY100EP11U Data sheet ( Hoja de datos )
| Número de pieza | SY100EP11U | |
| Descripción | 1:2 Differential Fanout Buffer | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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2.5V/3.3V/5V 1:2 DIFFERENTIAL
PECL/LVPECL/ECL
FANOUT BUFFER
ECL Pro™
SY10EP11U
SY100EP11U
FINAL
FEATURES
s 2.5V, 3.3V and 5V power supply options
s Guaranteed AC parameters over temperature:
• fMAX > 3.0GHz
• < 20ps output-to-output skew
• < 200ps tr / tf
• < 300ps propagation delay
s Wide temperature range: –40°C to +85°C
s Available in 8-pin (3mm) MSOP and SOIC packages
PIN CONFIGURATION/BLOCK DIAGRAM
ECL Pro™
DESCRIPTION
The SY10/100EP11U is a precision, high-speed 1:2
differential fanout buffer. Having within-device skews and
output transition times significantly improved over the
EL11V, the EP11U is ideally suited for those applications
which require the ultimate in AC performance.
The differential inputs of the EP11U employ clamping
circuitry to maintain stability under open input conditions.
If the inputs are left open, the Q outputs will go LOW.
Q0 1
/Q0 2
Q1 3
/Q1 4
VCC
75kΩ
8 VCC
7D
VEE
6 /D
75kΩ
VEE
75kΩ
VCC
5 VEE
VEE
8-pin MSOP and SOIC Packages
PIN NAMES
Pin
D
www.DataSheet4U.com
/D
Q0, /Q0
Q1, /Q1
VCC
VEE
Function
PECL, LVPECL, ECL, LVECL Clock or Data Input:
Internal 75kΩ pulldown resistor. If left floating,
pin defaults LOW, QOUT goes LOW.
PECL, LVPECL, ECL, LVECL complementary
Clock or Data Input: Internal 75kΩ pull-up and
down resistors. If left open, default is VCC/2. When
the input is not used, it can be left open.
PECL, LVPECL, ECL, LVECL Outputs:
Terminates to VCC –2V.
Positive Power Supply: Bypass with 0.1µF//0.01µF
low ESR capacitors.
Negative Power Supply: For PECL operation,
connect to GND.
CROSS REFERENCE TABLE
Micrel Semiconductor
SY10EP11UZI/KI
SY10EP11UZI/KI
SY100EP11UZI/KI
SY100EP11UZI/KI
ON Semiconductor
MC10EP11D/DT
MC10LVEP11D/DT
MC100EP11D/DT
MC100LVEP11D/DT
ECL Pro is a trademark of Micrel, Inc.
1
Rev.: D
Amendment: /0
Issue Date: March 2003
1 page  
Micrel
ECL Pro™
SY10EP11U
SY100EP11U
(100KEP) PECL DC ELECTRICAL CHARACTERISTICS(1)
VCC = 5.0V ±10%, VEE = 0V
Symbol
Parameter
TA = –40°C
TA = +25°C
Min. Typ. Max. Min. Typ. Max.
TA = +85°C
Min. Typ. Max. Unit Condition
VIL Input LOW Voltage
(Single-Ended)
3055 — 3375 3055 — 3375 3055 — 3375 mV
VIH Input HIGH Voltage
(Single-Ended)
3775 — 4120 3775 — 4120 3775 — 4120 mV
VOL
VOH
VIHCMR
Outuput LOW Voltage
Output HIGH Voltage
Input HIGH Voltage(2)
Common Mode Range
3055
3855
2.0
3180
3980
—
3305
4105
VCC
3055
3855
2.0
3180
3980
—
3305
4105
VCC
3055
3855
2.0
3180
3980
—
3305
4105
VCC
mV 50Ω to VCC–2V
mV 50Ω to VCC–2V
V
Note 1.
Note 2.
100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Input and output
parameters are at VCC = 5.0V. They vary 1:1 with VCC.
The VIHCMR range is referenced to the most positive side of the differential input signal. See “Input Waveform” section. Single-ended input
CLK pin operation is limited to VCC ≥ 3.0V in PECL mode.
(100KEP) ECL/LVECL DC ELECTRICAL CHARACTERISTICS(1)
VCC = 0V, VEE = –5.5V to –2.375V
Symbol
Parameter
TA = –40°C
TA = +25°C
TA = +85°C
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
VIL Input LOW Voltage
(Single-Ended)
–1945 — –1625 –1945 — –1625 –1945 — –1625 mV
VIH Input HIGH Voltage
(Single-Ended)
–1225 — –880 –1225 — –880 –1225 — –880 mV
VOL
VOH
VIHCMR
Outuput LOW Voltage
Output HIGH Voltage
Input HIGH Voltage(2)
Common Mode Range
–1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV 50Ω to VCC–2V
–1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV 50Ω to VCC–2V
VEE +1.2
0.0
VEE +1.2
0.0
VEE +1.2
0.0 V
Note 1.
Note 2.
100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.
The VIHCMR range is referenced to the most positive side of the differential input signal. See “Input Waveform” section. Single-ended input
CLK pin operation is limited to VEE ≤ –3.0V in ECL/LVECL mode.
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet SY100EP11U.PDF ] | |
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