SY100EP32V Datasheet PDF - Micrel Semiconductor
| Part Number | SY100EP32V | |
| Description | Pecl Divider | |
| Manufacturers | Micrel Semiconductor | |
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Micrel
5V/3.3V ÷ 2 DIVIDER
Precision Edge™
Precision ESYd1g0eE™P32V
SY1S0YE1P003E2PV32V
SY100EP32V
FINAL
FEATURES
s Guaranteed maximum frequency > 4GHz
s 3.3V and 5V power supply options
s Guaranteed propagation delay <440ps over
temperature
s Internal 75KΩ input pull-down resistors
DESCRIPTION
ECL Pro™
s Wide operating temperature range: –40°C to +85°C
s Available in 8-pin MSOP and SOIC packages
The SY10/100EP32V is an integrated ÷2 divider with
differential clock inputs.
The VBB pin, an internally generated voltage supply,
is available to this device only. For single-ended input
conditions, the unused differential input is connected to
VBB as a switching reference voltage. VBB may also rebias
AC-coupled inputs. When used, decouple VBB and VCC
via a 0.01µF capacitor and limit current sourcing or sinking
to 0.5mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the
PIN CONFIGURATION/BLOCK DIAGRAM
rising edge. Upon power-up, the internal flip-flops will
attain a random state; the reset allows for the
synchronous use of multiple EP32’s in a system.
The 100k series includes internal temperature
Reset 1
8 VCC
compensation circuitry.
www.DataSheet4U.com
R
CLK 2
7Q
÷2
PIN NAMES
/CLK 3
6 /Q
VBB 4
5 VEE
Pin
CLK, /CLK
Function
ECL Clock Inputs
TOP VIEW
(Available in MSOP or SOIC package)
Reset
VBB
Q, /Q
ECL Asynchronous Reset
Reference Voltage Output
ECL Data Outputs
TRUTH TABLE(1)
CLK
/CLK
RESET
XXZ
Z /Z L
Note 1:
Z = LOW-to-HIGH Transition
/Z = HIGH-to-LOW Transition
F = Divide by 2 function.
Q
L
F
/Q
H
F
Precision Edge and ECL Pro are trademarks of Micrel, Inc.
1
Rev.: C Amendment: /0
Issue Date: March 2003
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Micrel
Precision Edge™
SY10EP32V
SY100EP32V
(100EP) ECL/LVECL DC ELECTRICAL CHARACTERISTICS(1)
VCC = 0V; VEE = –3.3V to –5.0V ±10%(2)
TA = –40°C
TA = +25°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max.
TA = +85°C
Min. Typ. Max.
Unit
IEE Power Supply Current
VOH Output HIGH Voltage(3)
VOL Output LOW Voltage(3)
VIH Input HIGH Voltage
(Single-Ended)
—
–1145
–1945
–1225
—
–1020
–1820
—
37
–895
–1695
–880
—
–1145
–1945
–1225
30
–1020
–1820
—
37
–895
–1695
–880
—
–1145
–1945
–1225
—
–1020
–1820
—
42
–895
–1695
–880
mA
mV
mV
mV
VIL Input LOW Voltage
(Single-Ended)
–1945 — –1625 –1945 — –1625 –1945 — –1625 mV
VBB
VIHCMR
IIH
IIL
Output Voltage
Input HIGH Voltage(4)
Common Mode Range
(Differential)
Input HIGH Current
Input LOW Current
CLK
/CLK
–1525 –1425
VEE +2.0
—
0.5
–150
—
—
—
–1325
0.0
150
—
—
–1525 –1425
VEE +2.0
—
0.5
–150
—
—
—
–1325
0.0
150
—
—
–1525 –1425
VEE +2.0
—
0.5
–150
—
—
—
–1325
0.0
150
—
—
mV
V
µA
µA
Note 1.
Note 2.
Note 3.
Note 4.
100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.
Input and output parameters vary 1:1 with VCC.
All loading with 50Ω to VCC –2.0V.
VIHCMR (min) varies 1:1 with VEE. The VIHCMR range is referenced to the most positive side of the differential input signal.
TIMING DIAGRAM
CLK
RESET
Q
t
RR
5
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| Information | Total 8 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ SY100EP32V.PDF Datasheet ] | |
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