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부품번호 Z5380 기능
기능 SMALL COMPUTER SYSTEM INTERFACE
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Z5380 데이터시트, 핀배열, 회로
ZILOG Z5380 SCSI
PRODUCT SPECIFICATION
FEATURES
Z5380 SCSI
SMALL COMPUTER
SYSTEM INTERFACE (SCSI)
s Pin Compatible with the Industry Standard 5380
s Supports Target and Initiator Roles
s 40-Pin DIP or 44-Pin PLCC Package Styles
s Arbitration Support
s Low-Power CMOS
s DMA or Programmed I/O Data Transfers
s Asynchronous Interface (Supports 1.5 MB/s)
s Supports Normal or Block Mode DMA
s Direct SCSI Bus Interface with On-Board 48 mA Drivers s Memory or I/O Mapped CPU Interface
GENERAL DESCRIPTION
The Z5380 SCSI (Small Computer System Interface) con- detects a bus condition that requires attention. It also
troller is designed to implement the SCSI protocol as supports arbitration and reselection. The Z5380 has the
defined by the ANSI X3.131-1986 standard, and is fwuwwll.DyataSheetp4Ur.coomper hand-shake signals to support normal and block
compatible with the industry standard 5380. It is capable mode DMA operations with most DMA controllers avail-
of operating both as a Target and as an Initiator. Special able (Figure 2).
high-current open-drain outputs enable the Z5380 to di-
rectly interface to, and drive, the SCSI bus. The Z5380 has Notes:
the necessary interface hook-ups which allows the system
CPU to communicate with it like any other peripheral
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
device. The CPU can read from, or write to, the SCSI
registers which are addressed as standard or memory- Power connections follow conventional descriptions below:
mapped I/Os (Figure 1).
Connection
Circuit
Device
The Z5380 increases the system performance by minimiz-
ing the CPU intervention in DMA operations which the SCSI
controls. The CPU is interrupted by the SCSI when it
Power
Ground
VCC
GND
VDD
VSS
PS97SCC0100
PS009101-0201
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Z5380 pdf, 반도체, 판매, 대치품
ZILOG Z5380 SCSI
PIN DESCRIPTION (Continued)
IRQ Interrupt Request (Output, Active High). IRQ alerts a
microprocessor of an error condition or an event comple-
tion.
READY Ready (Output, Active High). Ready is used to
control the speed of Block Mode DMA transfers. This
signal goes active to indicate the chip is ready to send/
receive data and remains Low after a transfer until the last
byte is sent or until the DMA Mode bit is reset.
/RESET Reset (Input, Active Low). /RESET clears all reg-
isters. It has no effect upon the SCSI /RST signal.
SCSI Bus
The following signals are all bi-directional, active Low,
open-drain, with 48 mA sink capability. All pins interface
directly with the SCSI bus.
/ACK Acknowledge (Bi-directional, Open-drain, Active
Low). Driven by an Initiator, /ACK indicates an acknowl-
edgment for a /REQ//ACK data-transfer handshake. In the
Target role, /ACK is received as a response to the /REQ
signal.
/ATN Attention (Bi-directional, Open-drain, Active Low).
Driven by an Initiator, received by the Target, /ATN indi-
cates an Attention condition.
/BSY Busy (Bi-directional, Open-drain, Active Low). This
signal indicates that the SCSI bus is being used and can
be driven by both the Initiator and the Target device.
/DB7-/DB0, /DBP Data Bus Bits, Data Bus Parity Bit (Bi-
directional, Open-drain). These eight data bits (/DB7-/
DB0), plus a parity bit (/DBP) form the data bus. /DB7 is the
most significant bit (MSB) and has the highest priority
during the Arbitration phase. Data parity is odd. Parity is
always generated and optionally checked. Parity is not
valid during Arbitration.
I//O Input/Output (Bi-directional, Open-drain). I/O is a
signal driven by a Target which controls the direction of
data movement on the SCSI bus. True indicates input to the
Initiator. This signal is also used to distinguish between
Selection and Reselection phases.
/MSG Message (Bi-directional, Open-drain, Active Low).
This signal is driven by the Target during the Message
phase. This signal is received by the Initiator.
/REQ Request (Bi-directional, Open-drain, Active Low).
Driven by the Target and received by the Initiator, this
signal indicates a request for a /REQ//ACK data-transfer
handshake.
/RST SCSI Bus Reset (Bi-directional, Open-drain, Active
Low). This signal indicates a SCSI bus Reset condition.
/SEL Select (Bi-directional, Open-drain, Active Low). This
signal is used by an Initiator to select a Target, or by a
Target to reselect an Initiator.
C//D Control/Data (Bi-directional, Open-drain). Driven by
the Target and received by the Initiator, C//D indicates
whether Control or Data information is on the Data Bus.
True indicates Control.
FUNCTIONAL DESCRIPTION
The Z5380 Small Computer System Interface (SCSI) has a
set of eight registers that are controlled by the CPU. By
reading and writing the appropriate registers, the CPU
may initiate any SCSI Bus activity or may sample and
assert any signal on the SCSI Bus. This allows the user to
implement all or any of the SCSI protocol in software. These
registers are read (written) by activating /CS with an
address on A2-A0 and then issuing an /IOR (/IOW) pulse.
This section describes the operation of the internal regis-
ters (Table 1).
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PS009101-0201
PS97SCC0100

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Z5380 전자부품, 판매, 대치품
ZILOG Z5380 SCSI
the SCSI Bus. The /RST signal will remain asserted until this
bit is reset or until an external /RESET occurs. After this bit
is set (1), IRQ goes active and all internal logic and control
registers are reset (except for the interrupt latch and the
Assert /RST bit). Writing a zero to bit 7 of the Initiator
Command Register deasserts the /RST signal. The status
of this bit is monitored by reading the Initiator Command
Register.
Mode Register. Address 2 (Read/Write). The Mode Reg-
ister controls the operation of the chip. This register deter-
mines whether the Z5380 operates as an Initiator or a
Target, whether DMA transfers are being used, whether
parity is checked, and whether interrupts are generated on
various external conditions. This register is read to check
the value of these internal control bits (Figure 8).
Address: 2
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Arbitrate
DMA Mode
Monitor /BSY
Enable /EOP Interrupt
Enable Parity Interrupt
Enable Parity Checking
Target Mode
Block Mode DMA
Figure 8. Mode Register
Receive Register and set (0) for Start DMA Initiator Receive
Register. The control bit Assert Data Bus (Initiator Com-
mand Register, bit 0) must be True (1) for all DMA send
operations. In the DMA mode, /REQ and /ACK are auto-
matically controlled.
The DMA Mode bit is not reset upon the receipt of an /EOP
signal. Any DMA transfer is stopped by writing a zero into
this bit location; however, care must be taken not to cause
/CS and /DACK to be active simultaneously.
Bit 2. Monitor Busy. The Monitor Busy bit, when True (1),
causes an interrupt to be generated for an unexpected
loss of /BSY. When the interrupt is generated due to loss of
/BSY, the lower six bits of the Initiator Command Register
are reset (0) and all signals are removed from the SCSI
Bus.
Bit 3. Enable /EOP interrupt. The enable /EOP interrupt bit,
when set (1), causes an interrupt to occur when the /EOP
(End Of Process) signal is received from the DMA con-
troller logic.
Bit 4. Enable Parity Interrupt. The Enable Parity Interrupt
bit, when set (1), will cause an interrupt (IRQ) to occur if a
parity error is detected. A parity interrupt will only be
generated if the Enable Parity Checking bit (bit 5) is also
enabled (1).
Bit 5. Enable Parity Checking. The Enable Parity Checking
bit determines whether parity errors are ignored or saved
in the parity error latch. If this bit is reset (0), parity is
ignored. Conversely, if this bit is set (1), parity errors are
saved.
The following describes the operation of all bits in the
Initiator Command Register:
Bit 0. Arbitrate. The Arbitrate bit is set (1) to start the
Arbitration process. Prior to setting this bit, the Output Data
Register should contain the proper SCSI device ID value.
Only one data bit should be active for SCSI Bus Arbitration.
The Z5380 waits for a Bus-Free condition before entering
the Arbitration phase. The results of the Arbitration phase
is determined by reading the status bits LA and AIP
(Initiator Command Register, bits 5 and 6, respectively).
Bit 1. DMA Mode. The DMA Mode bit is normally used to
enable a DMA transfer and must be set (1) prior to writing
Start DMA Send Register, Start DMA Target Register, and
Start DMA Initiator Receiver Register. These three regis-
ters are used to start DMA transfers. The Target Mode bit
(Mode Register, bit 6) must be consistent with writes to
Start DMA Target Receive and Start DMA Initiator Receive
Registers; i.e., set (1) for a write to Start DMA Target
Bit 6. Target Mode. The Target Mode bit allows the Z5380
to operate as a SCSI Bus Initiator or Target. With this bit
reset (0), the Z5380 operates as a SCSI Bus Initiator.
Setting Target Mode bit to 1 programs the Z5380 to
operate as a SCSI Bus Target device. If the signals /ATN
and /ACK are to be asserted on the SCSI Bus, the Target
Mode bit must be reset (0). If the signals C//D, I//O, /MSG,
and /REQ are to be asserted on the SCSI Bus, the Target
Mode bit must be set (1).
Bit 7. Block Mode DMA. The Block Mode DMA bit controls
the characteristics of the DMA DRQ-/DACK handshake.
When this bit is reset (0) and the DMA Mode bit is active (1),
the DMA handshake uses the normal interlocked hand-
shake, and the rising edge of /DACK indicates the end of
each byte being transferred. In Block Mode operation,
when the Block Mode DMA bit is set (1) and DMA Mode bit
is active (1), the end of /IOR or /IOW signifies the end of
each byte transferred and /DACK is allowed to remain
active throughout the DMA operation. Ready can then be
used to request the next transfer.
PS97SCC0100
PS009101-0201
7

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SMALL COMPUTER SYSTEM INTERFACE

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