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PDF SY100E111AL Data sheet ( Hoja de datos )
| Número de pieza | SY100E111AL | |
| Descripción | 1:9 DIFFERENTIAL CLOCK DRIVER | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Micrel, Inc.
5V/3.3V 1:9 DIFFERENTIAL
CLOCK DRIVER (w/o ENABLE)
Precison Edge®
PrecisioSnSYY1E0100dEEg11e1111®AA//LL
SY10E111A/L
SY100E111A/L
FEATURES
s 5V and 3.3V power supply options
s 200ps part-to-part skew
Precision Edge®
s 50ps output-to-output skew
s Differential design
DESCRIPTION
s VBB output
The SY10/100E111A/L are low skew 1-to-9 differential
s Voltage and temperature compensated outputs
driver designed for clock distribution in mind. The
s 75KΩ input pulldown resistors
s Fully compatible with Motorola MC100LVE111
s Available in 28-pin PLCC package
SY10/100E111A/L's function and performance are similar to
the popular SY10/100E111, with the improvement of lower
jitter and the added feature of low voltage operation. It accepts
one signal input, which can be either differential or single-
BLOCK DIAGRAM
ended if the VBB output is used. The signal is fanned out to 9
identical differential outputs.
The E111A/L are specifically designed, modeled and
produced with low skew as the key goal. Optimal design and
Q0 layout serve to minimize gate to gate skew within a device, and
Q0 empirical modeling is used to determine process control limits
that ensure consistent t distributions from lot to lot. The net
Q1
pd
result is a dependable, guaranteed low skew device.
Q1 To ensure that the tight skew specification is met it is
Q2 necessary that both sides of the differential output are
Q2 www.DataSheette4Ur.cmominated into 50Ω, even if only one side is being used. In
Q3 most applications, all nine differential pairs will be used and
Q3 therefore terminated. In the case where fewer that nine pairs
are used, it is necessary to terminate at least the output pairs
IN Q4 on the same package side as the pair(s) being used on that
IN Q4 side, in order to maintain minimum skew. Failure to do this will
Q5 result in small degradations of propagation delay (on the order
Q5 of 10-20ps) of the output(s) being used which, while not being
catastrophic to most designs, will mean a loss of skew margin.
Q6
The E111A/L, as with most other ECL devices, can be
Q6
Q7
operated from a positive V supply in PECL mode. This
CC
allows the E111A/L to be used for high performance clock
Q7 distribution in +5V/+3.3V systems. Designers can take
Q8 advantage of the E111A/L's performance to distribute low
VBB Q8 skew clocks across the backplane or the board. In a PECL
environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For
systems incorporating GTL, parallel termination offers the
lowest power by taking advantage of the 1.2V supply as
PIN NAMES
terminating voltage.
Pin
IN, IN
Q0, Q0 — Q8, Q8
VBB
VCCO
Function
Differential Input Pair
Differential Outputs
VBB Output
VCC to Output
Precision Edge is a registered trademark of Micrel, Inc.
M9999-032006
[email protected] or (408) 955-1690
1
Rev.: J
Amendment: /0
Rev. Date: March 2006
1 page  
Micrel, Inc.
Precison Edge®
SY10E111A/L
SY100E111A/L
AC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = -40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
tPD Propagation Delay to Output
ps
IN (differential), Note 2
380 — 680 430 — 630 430 — 630 430 — 630
IN (single-ended), Note 3
280 — 780 330 — 730 330 — 730 330 — 730
tskew Within-Device Skew, Note 4
Part-to-Part Skew (Diff.)
— — 75 — — 50 — — 50 — — 50 ps
— — 250 — — 200 — — 200 — — 200
VPP
VCMR
tr
tf
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Minimum Input Swing, Note 5
Common Mode Range, Note 6
Rise/Fall Times
20% to 80%
250 — — 250 — — 250 — — 250 — — mV
–1.5 — –0.4 –1.5 — –0.4 –1.5 — –0.4 –1.5 — –0.4 V
200 — 650 200 — 600 200 — 600 200 — 600 ps
Parametric values specified at:
5 volt Power Supply Range 100E111A Series:
-4.2V to -5.5V.
10E111A Series
-4.75V to -5.5V.
3 volt Power Supply Range 10/100E111L Series:
-3.0V to -3.8V.
The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
VPP (min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP (min) is AC
limited for the E111A/L as a differential input as low as 50mV will still produce full ECL levels at the output.
VCMR is defined as the range within the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min).
For PECL operation: VCMR (max) = VCC – |VCMR (max)| and VCMR (min) = VCC – |VCMR (min)|
M9999-032006
[email protected] or (408) 955-1690
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet SY100E111AL.PDF ] | |
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