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PDF A3992 Data sheet ( Hoja de datos )
| Número de pieza | A3992 | |
| Descripción | DMOS Dual Full-Bridge Microstepping PWM Motor Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Features and Benefits
▪ ±1.5 A, 50 V continuous output rating
▪ Low RDS(on) DMOS output drivers
▪ Short-to-ground protection
▪ Shorted load protection
▪ Optimized microstepping via six bit linear DACs
▪ Programmable mixed, fast, and slow current decay modes
▪ 4 MHz internal oscillator for digital timing
▪ Serial interface controls chip functions
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Crossover-current protection
▪ Inputs compatible with 5 or 3.3 V control signals
▪ Sleep and Idle modes
Packages
24 pin batwing DIP (suffix B) and 24 pin TSSOP with
exposed thermal pad (suffix LP)
Description
Designed for pulse width modulated (PWM) current control of
bipolar microstepped stepper motors, the A3992 is capable of
continuous output currents to ±1.5 A and operating voltages to
50 V. Internal fixed off-time PWM current control timing circuitry
can be programmed via the serial interface to operate in slow, fast,
or mixed decay modes.
The desired load current level is set via the serial port with two
six bit linear DACs in conjunction with a reference voltage. The
six bits of control allow maximum flexibility in torque control for
a variety of step methods, from microstepping to full step drive.
Load current is set in 1.56% increments of the maximum value.
Synchronous rectification circuitry allows the load current to flow
through the low RDS(on) of the DMOS output driver during current
decay. This feature eliminates the need for external clamp diodes
in most applications, saving cost and external component count,
while minimizing power dissipation.
Internal circuit protection includes short-to-ground, shorted load,
thermal shutdown with hysteresis, and crossover current protection.
Special power up sequencing is not required.
LP package approximate scale
The A3992 is supplied in a thin profile (1.2 mm maximum height)
24 pinwww.DataSheet4U.com TSSOP (suffix LP) with exposed thermal pad and a 24 pin
plastic DIP with dual copper batwing tabs (suffix B). The exposed
thermal pad on the LPis at ground potential and needs no electrical
isolation. Both packages are lead (Pb) free with 100% matte tin
leadframe plating.
Typical Application
Microcontroller or
Controller Logic
10 μF
5 kΩ
0.22 μF
VREG
VDD
0.22 μF
CP1
CP2
VCP
ROSC
CLOCK
A3992
DATA
STROBE
REF
SLEEP
VBB1
VBB2
OUT1A
OUT1B
SENSE1
OUT2A
OUT2B
SENSE2
0.22 μF
100 μF
0.1 μF
0.1 μF
3992DS
1 page  
A3992
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
Serial Interface Description
The A3992 is controlled via a 3 wire serial port. The
programmable functions allow maximum flexibility in
configuring the PWM to the motor drive requirements.
The serial data is written as two 19 bit words, 1 bit
to select which word (referred to here as Word 0 and
Word 1) and 18 bits of data. The serial port is defined
in the following tables and text descriptions.
Word 0 Bit Assignments
Word 0 is selected by setting D0 = 0. Assignments are
summarized in the following table, and desribed in
detail in the remainder of this section.
Word 0 Bit Assignments
Bit Function
D0 Word Select = 0
D1 Bridge 1, DAC, LSB
D2 Bridge 1, DAC, Bit2
D3 Bridge 1, DAC, Bit3
D4 Bridge 1, DAC, Bit4
D5 Bridge 1, DAC, Bit 5
D6 Bridge 1, DAC, MSB
D7 Bridge 2, DAC, LSB
D8 Bridge 2, DAC, Bit2
D9 Bridge 2, DAC, Bit3
D10 Bridge 2, DAC, Bit4
D11 Bridge 2, DAC, Bit 5
D12 Bridge 2, DAC, MSB
D13 Bridge 1 Phase
D14 Bridge 2 Phase
D15 Bridge 1 Mode
D16 Bridge 2 Mode
D17 Reference Select
D18 Range Select
D1 – D6 Bridge 1, Linear DAC. 6 bit word to set de-
sired current level for bridge 1. Setting all bits to zero
disables Full Bridge 1, all drivers off. (See Current
Regulation in the Functional Description section.)
D7 – 12 Bridge 2 Linear DAC. 6 bit word to set the
desired current level for bridge 2. Setting all bits to
zero disables Full Bridge 2, all drivers off. (See Cur-
rent Regulation in the Functional Description section.)
D13 Bridge 1 Phase. This bit controls the direction
of current for motor phase 1 as defined below:
D13 OUT1A OUT1B
0L
H
1H
L
D14 Bridge 2 Phase. This bit controls the direction
of current for motor phase 2 as defined below:
D14 OUT2A OUT2B
0 LH
1HL
D15 Bridge 1 Mode. This bit determines the decay
for Full Bridge 1 as defined below:
D15 Mode
0 Mixed Decay
1 Slow Decay
D16 Bridge 2 Mode. This bit determines the decay
for Full Bridge 2 as defined below:
D16 Mode
0 Mixed Decay
1 Slow Decay
D17 Ref Select. This bit determines the reference
input for the two 6 bit linear DACs. Logic low selects
internal 2 V reference voltage, logic high selects ex-
ternal reference input on the REF pin.
D18 Gm Range Select. D18 determines if the scaling
factor used is 4 or 8:
D18 Divider
0 ÷8
1 ÷4
Load Current
ITRIP = VDAC/(RSENSE × 8)
ITRIP = VDAC/(RSENSE × 4)
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5 Page 
A3992
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
Device Pin-out Diagrams
B Package
VCP 1
CP1 2
CP2 3
OUT1B 4
VBB1 5
GND 6
GND 7
SENSE1 8
OUT1A 9
STROBE 10
CLOCK 11
DATA 12
24 OSC
23 SLEEP
22 VREG
21 OUT2B
20 VBB2
19 GND
18 GND
17 SENSE2
16 OUT2A
15 VDD
14 MUX
13 REF
LP Package
SENSE1 1
OUT1A 2
NC 3
STROBE 4
CLOCK 5
DATA 6
GND 7
REF 8
MUX 9
VDD 10
OUT2A 11
SENSE2 12
PAD
24 VBB1
23 NC
22 OUT1B
21 CP2
20 CP1
19 VCP
18 GND
17 OSC
16 SLEEP
15 VREG
14 OUT2B
13 VBB2
Terminal List Table
Number
B LP
Package Package
1 19
2 20
3 21
4 22
5 24
6, 7, 18, 19
7, 18
81
92
10 4
11 5
12 6
13 8
14 9
15 10
16 11
17 12
20 13
21 14
22 15
23 16
24 17
– 3, 23
––
Name
VCP
CP1
CP2
OUT1B
VBB1
GND
SENSE1
OUT1A
STROBE
CLOCK
DATA
REF
MUX
VDD
OUT2A
SENSE2
VBB2
OUT2B
VREG
SLEEP
OSC
NC
PAD
Pin Description
Reservoir capacitor terminal
Charge pump capacitor terminal
Charge pump capacitor terminal
DMOS Full Bridge 1, output B
Load supply
Ground. On B package, internally fused to the die pad
for enhanced thermal dissipation.
Sense resistor terminal for Full Bridge 1
DMOS Full Bridge 1, output A
Logic input
Logic input
Logic input
Gm reference input
Not used
Logic supply
DMOS Full Bridge 2, output A
Sense resistor terminal for Full Bridge 2
Load supply
DMOS Full Bridge 2, output B
Internal regulator
Logic input
Oscillator input
No connection
Exposed thermal pad for enhanced thermal dissipation.
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet A3992.PDF ] | |
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