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PDF SY58608U Data sheet ( Hoja de datos )
| Número de pieza | SY58608U | |
| Descripción | 1:2 LVDS Fanout Buffer | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SY58608U
3.2Gbps Precision, 1:2 LVDS Fanout Buffer
with Internal Termination and Fail Safe Input
General Description
The SY58608U is a 2.5V, high-speed, fully differential
1:2 LVDS fanout buffer optimized to provide two
Precision Edge®
identical output copies with less than 20ps of skew and
less than 10psPP total jitter. The SY58608U can process
clock signals as fast as 2GHz or data patterns up to
3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVPP) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (VREF-AC) is provided to bias the VT pin.
The outputs are 325mV LVDS, with rise/fall times
guaranteed to be less than 100ps.
Features
• Precision 1:2, 325mV LVDS fanout buffer
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <300ps propagation delay (IN-to-Q)
– <20ps within-device skew
– <100ps rise/fall times
• Fail Safe Input
– Prevents outputs from oscillating when input is
invalid
The SY58608U operates from a 2.5V ±5% supply and is • Ultra-low jitter design
guaranteed over the full industrial temperature range
– <1psRMS cycle-to-cycle jitter
(–40°C to +85°C). For applications that require CML or
–
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<10psPP total jitter
<1psRMS random jitter
<10psPP deterministic jitter
Micrel’s high-speed, Precision Edge® product line.
• High-speed LVDS outputs
Data sheets and support documentation can be found • 2.5V ±5% power supply operation
on Micrel’s web site at: www.micrel.com.
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) MLF® package
Functional Block Diagram
Applications
• All SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
• Backplane distribution
Markets
• DataCom
• Telecom
• Storage
• ATE
• Test and Measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2006
M9999-102706-A
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
SY58608U
AC Electrical Characteristics(8)
VCC = +2.5V ±5%, RL = 100Ω across the output pairs, Input tr/tf: ≤300ps; TA = –40°C to +85°C,
unless otherwise stated.
Symbol Parameter
Condition
Min
fMAX
tPD
tSkew
Maximum Frequency
Propagation Delay IN-to-Q
Within Device Skew
NRZ Data
VOUT > 200mV
VIN: 100mV-200mV
VIN: 200mV-800mV
Note 9
Clock
3.2
2
170
130
Part-to-Part Skew
Note 10
tJitter
Data
Random Jitter
Note 11
Deterministic Jitter Note 12
Clock
Cycle-to-Cycle Jitter Note 13
Total Jitter
Note 14
tr, tf Output Rise/Fall Time
(20% to 80%)
At full output swing.
35
Typ
4.25
3
280
200
5
60
Max
420
300
20
135
1
10
1
10
100
Units
Gbps
GHz
ps
ps
ps
ps
psRMS
psPP
psRMS
psPP
ps
Duty Cycle
Differential I/O
47 53 %
Notes:
8. These high-speed parameters are Guaranteed by design and characterization.
9. Within-device skew is measured between two different outputs under identical input transitions.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
12. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
13. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
14. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
October 2006
5 M9999-102706-A
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Input Interface Applications
SY58608U
Figure 4a. CML Interface
(DC-Coupled)
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
(DC-Coupled)
Related Product and Support Documents
Part Number
SY58606U
SY58607U
HBW Solutions
Function
4.25Gbps Precision, 1:2 CML Fanout
Buffer with Internal Termination and Fail
Safe Input
3.2Gbps Precision, 1:2 LVPECL Fanout
Buffer with Internal Termination and Fail
Safe Input
New Products and Termination Application
Notes
Data Sheet Link
http://www.micrel.com/page.do?page=/product-
info/products/sy58606u.shtml
http://www.micrel.com/page.do?page=/product-
info/products/sy58607u.shtml
http://www.micrel.com/product-info/products/sy89830u.shtml
October 2006
11 M9999-102706-A
[email protected] or (408) 955-1690
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet SY58608U.PDF ] | |
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