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부품번호 FAN5033 기능
기능 Synchronous Buck Controller
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FAN5033 데이터시트, 핀배열, 회로
January 2007
FAN5033
8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller
Features
Description
ƒ Selectable 2- or 3-phase operation at up to 1MHz
per phase
ƒ ±7.7mV worst-case differential sensing error over
The FAN5033 device is a multi-phase buck switching
regulator controller optimized to convert a 12V input
supply to the processor core voltage required by high
performance Intel® processors. It has an internal 8-bit
temperature
DAC that converts a digital voltage identification (VID)
ƒ Active current balancing between the output phases
ƒ Power Good and Crowbar blanking supports
code, sent from the processor, to set the output voltage
between 0.5V and 1.6V in 6.25mV steps. It outputs
PWM signals to external MOSFET drivers that drive the
on-the-fly VID code changes
switching power MOSFETs. The switching frequency of
ƒ 0.5V to 1.6V output
the design is programmable by a single resistor value.
The number of phases can be programmed to support
ƒ Fully compliant with the Intel® VR10 and VR11
two- or three-phase applications.
specifications
The FAN5033 also includes programmable no-load
ƒ Selectable VR10 extended (7-bit) and VR11 (8-bit)
offset and droop functions to adjust the output voltage
VID tables
as awww.DataSheet4U.com function of the load current, as required by the Intel
ƒ Programmable soft-start ramp
ƒ Programmable short-circuit protection and
specifications. The FAN5033 provides an accurate and
reliable short-circuit protection function with an
adjustable over-current set point.
latch-off delay
The FAN5033 is specified over the commercial
Applications
temperature range of 0°C to +85°C and is available in a
32-lead MLP package.
ƒ Desktop PC/Server processor power supplies for
existing and next-generation Intel processors
ƒ VRM modules
Ordering Information
Part Number Temperature Range Pb-Free Package Type Packing Method Quantity
FAN5033MPX
0°C to 85°C
Yes MLP-32 Tape and Reel 3,000 per Reel
Intel® is a registered trademark of Intel Corporation.
© 2007 Fairchild Semiconductor 2006
FAN5033 Rev. 1.0.0
www.fairchildsemi.com




FAN5033 pdf, 반도체, 판매, 대치품
Pin #
14
15
16
17 to 19
20 to 22
23
24 to 31
32
-
Name
GND
OD
NC
SW3 to
SW1
PWM3 to
PWM1
VCC
VID7 to
VID0
VIDSEL
Exposed
Paddle
Description
Ground. All internal biasing and logic output signals of the device are referenced to this
ground.
Output Disable. This pin is actively pulled low when the EN input is low or when VCC is
below its UVLO threshold to disable the external MOSFET drivers. (Also referred to as
OD# in the text of this document.)
No Connection. This pin is not connected internally.
Switching Node Current Balance Inputs. Sense the switching side of the inductor and
used to measure the current level in each phase. The SW pins of unused phases should
be left open.
PWM Outputs. Each output is connected to the input of an external MOSFET driver,
such as the FAN5109. Connecting the PWM3 output to VCC disables that phase,
allowing the FAN5033 to operate as a two-phase controller.
Supply Voltage for the Device.
Voltage Identification Code Inputs. These digital inputs are connected to the internal
DAC and used to program the output voltage. These pins have 1µA internal pull-down;
so if they are left open, the input state is decoded as logic low.
VID Table Select Input. A logic low selects the extended VR10 DAC table and a logic
high selects the VR11 DAC table. This pin has a 1µA internal pull-down; so if left open,
the input state is decoded as logic low.
Internally connected to die ground. May be connected to ground or left floating.
Connect to ground for lowest package thermal resistance.
© 2006 Fairchild Semiconductor 2006
FAN5033 Rev. 1.0.0
4 of 39
www.fairchildsemi.com

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FAN5033 전자부품, 판매, 대치품
Electrical Characteristics (Continued)
VCC = 12V, FBRTN = GND, and TA = +25°C. The denotes specifications that apply over the full operating
temperature range.
Symbol
Parameter
Current Sense Amplifier
VOS(CSA) Offset Voltage
IBIAS(CSSUM) Input Bias Current (for CSSUM)
IBIAS(CSREF) Input Current (for CSREF)
GBW(CSA)
Gain Bandwidth Product
Slew Rate
VCSACM Input Common-Mode Range
Output Voltage Range
ICSCOMP Output Current
tOC(DELAY) Current Limit Latch-off Delay Time
Current Balance Circuit
VSW(x)CM Common Mode Range(2)
RSW(x)
Input Resistance
ISW(x)
Input Current
ΔISW(x)
Input Current Matching
Current Limit Comparator
VILIMIT
Output Voltage
IILIMIT
Output Current
Maximum Output Current
VCL Current Limit Threshold Voltage
Current Limit Setting Ratio
Delay Timer
IDELAY
Normal Mode Output Current
IDELAY(CL) Output Current in Current Limit
VDELAY(TH) Threshold Voltage
Soft-Start
I(SS) Output Current
Enable Input
VTH(EN) Threshold Voltage
VHYS(EN) Threshold Hysteresis
IIN(EN)
Enable Input Current
tDELAY(EN) Turn-on Delay
Conditions
Min. Typ. Max. Unit
CSSUM – CSREF
Figure 4
Current drawn by
CSREF Pin
CSSUM = CSCOMP(2)
CCSCOMP = 10pF(2)
CSSUM and CSREF
CDELAY = 10nF
-1.0
+1.0 mV
-50
+50 nA
-3
+3 µA
0
0.05
10
10
1
5
MHz
V/µs
3.2 V
3.2 V
mA
ms
SW(x) = 0V
SW(x) = 0V
SW(x) = 0V
-600
35
1.6
-5
+200
50 65
3.3 5.0
+5
mV
kΩ
µA
%
RILIMT = 143kΩ
1.6 1.7 1.8
V
RILIMT = 143kΩ
12 µA
60
µA
VCSREF VCSCOMP, RILIMT
= 143kΩ
100
120
140
mV
VCL / IILIMT
10 mV/µA
12 15 18
3.0 3.75 4.5
1.6 1.7 1.8
µA
µA
V
During Start-up
12 15 18 µA
Start-up sequence,
EN>950mV, CDELAY =
10nF
800 850 900
80 100 120
1
2
mV
mV
µA
ms
© 2006 Fairchild Semiconductor 2006
FAN5033 Rev. 1.0.0
7 of 39
www.fairchildsemi.com

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