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FDD6N50 데이터시트 PDF




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부품번호 FDD6N50 기능
기능 N-Channel MOSFET
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


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FDD6N50 데이터시트, 핀배열, 회로
FDD6N50 / FDU6N50
N-Channel UniFETTM MOSFET
500 V, 6 A, 900 mΩ
Features
• RDS(on) = 900 mΩ (Max.) @ VGS = 10 V, ID = 3 A
• Low Gate Charge (Typ. 12.8 nC)
• Low Crss (Typ. 9 pF)
• 100% Avalanche Tested
• Improved dv/dt Capability
Applications
• LCD/LED/PDP TV
• Lighting
• Uninterruptible Power Supply
• AC-DC Power Supply
D
November 2013
Description
UniFETTM MOSFET is Fairchild Semiconductor’s high voltage
MOSFET family based on planar stripe and DMOS technology.
This MOSFET is tailored to reduce on-state resistance, and to
provide better switching performance and higher avalanche
energy strength. This device family is suitable for switching
power converter applications such as power factor correction
(PFC), flat panel display (FPD) TV power, ATX and electronic
lamp ballasts.
D
G
S
D-PAK
GDS
I-PAK
Absolute Maximum Ratings TC = 25oC unless otherwise noted.
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
(Note 1)
Gate-Source voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation
(TC = 25°C)
- Derate Above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8” from Case for
5 Seconds
G
S
FDD6N50TM /
FDD6N50TM_WS /
FDU6N50TU
500
6
3.8
24
±30
270
6
8.9
4.5
89
0.71
-55 to +150
300
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Thermal Characteristics
Symbol
RθJC
RθJA
Parameter
Thermal Resistance, Junction-to-Case, Max.
Thermal Resistance, Junction-to-Ambient, Max.
©2006 Fairchild Semiconductor Corporation
FDD6N50 / FDU6N50 Rev. C1
1
FDD6N50TM /
FDD6N50TM_WS /
FDU6N50TU
1.4
83
Unit
°C/W
www.fairchildsemi.com




FDD6N50 pdf, 반도체, 판매, 대치품
Typical Performance Characteristics (Continued)
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
1.2
1.1
1.0
0.9
0.8
-100
Notes :
1. VGS = 0 V
2. ID = 250 μA
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 9. Maximum Safe Operating Area
102 Operation in This Area
is Limited by R DS(on)
101
100
10 us
100 us
1 ms
10 ms
DC
Notes :
10-1
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
10-2
100
101 102
VDS, Drain-Source Voltage [V]
103
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-100
Notes :
1. VGS = 10 V
2. ID = 3 A
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 10. Maximum Drain Current
vs. Case Temperature
8
6
4
2
0
25 50 75 100 125 150
TC, Case Temperature []
Figure 11. Transient Thermal Response Curve
100
D = 0 .5
0.2
0.1
1 0 -1
0.05
0.02
0.01
1 0 -2
1 0 -5
N otes :
1 . Z θ JC(t) = 1 .4 /W M a x.
2. D uty Factor, D =t1/t2
3 . T JM - T C = P D M * Z θ JC(t)
PDM
t1
t2
single pulse
1 0 -4
1 0 -3
1 0 -2
10 -1
100
t1, S quare W ave P ulse D uration [sec]
101
©2006 Fairchild Semiconductor Corporation
FDD6N50 / FDU6N50 Rev. C1
4
www.fairchildsemi.com

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FDD6N50 전자부품, 판매, 대치품
Mechanical Dimensions
Figure 16. TO252 (D-PAK), Molded, 3-Lead, Option AA&AB
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT252-003
©2006 Fairchild Semiconductor Corporation
FDD6N50 / FDU6N50 Rev. C1
7
www.fairchildsemi.com

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