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부품번호 | FDS8876 기능 |
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기능 | N-Channel MOSFET | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 12 페이지수
April 2007
FDS8876
N-Channel PowerTrench® MOSFET
30V, 12.5A, 8.2mΩ
tm
Features
rDS(on) = 8.2mΩ, VGS = 10V, ID = 12.5A
rDS(on) = 10.2mΩ, VGS = 4.5V, ID = 11.4A
High performance trench technology for extremely low
rDS(on)
Low gate charge
High power and current handling capability
RoHS Compliant
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
rDS(on) and fast switching speed.
Applications
DC/DC converters
Branding Dash
1
2
3
4
SO-8
5
54
63
72
81
©2007 Fairchild Semiconductor Corporation
FDS8876 Rev. B
1
www.fairchildsemi.com
Typical Characteristics TJ = 25°C unless otherwise noted
1.2 16
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
12
VGS = 10V
8
VGS = 4.5V
4
RθJA=50oC/W
0
25 50 75 100 125
TA, AMBIENT TEMPERATURE (oC)
150
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
2
1
0.1
0.01
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
0.0005
10-4
SINGLE PULSE
RθJA = 125oC/W
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
102
103
2000
1000
100
VGS = 10V
SINGLE PULSE
RθJA = 125oC/W
TA = 25oC
10
1
0.5
10-4
10-3 10-2 10-1 100
t, PULSE WIDTH (s)
101
Figure 4. Single Pulse Maximum Power Dissipation
102
103
©2007 Fairchild Semiconductor Corporation
FDS8876 Rev. B
4
www.fairchildsemi.com
4페이지 Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01Ω
0
tP
IAS
BVDSS
VDS
VDD
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VGS
Ig(REF)
VDS
L
DUT
+
VDD
-
Figure 17. Gate Charge Test Circuit
VDD
Qgs2
Qg(TOT)
VDS
Qg(5)
VGS
VGS = 10V
VGS = 5V
VGS = 1V
0
Qg(TH)
Qgs
Ig(REF)
0
Qgd
Figure 18. Gate Charge Waveforms
VDS
RL
VGS
VGS
RGS
DUT
+
VDD
-
Figure 19. Switching Time Test Circuit
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
Figure 20. Switching Time Waveforms
©2007 Fairchild Semiconductor Corporation
FDS8876 Rev. B
7
www.fairchildsemi.com
7페이지 | |||
구 성 | 총 12 페이지수 | ||
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