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EIB-TP-UART-IC PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EIB-TP-UART-IC
기능 TP-UART-IC
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EIB-TP-UART-IC 데이터시트, 핀배열, 회로
TECHNICAL DATA
EIB-TP-UART-IC
VB -
Tx0
Rx IN
MODE 0
MODE 1
TEST MODE
X1
X2
TSTOUT
RxD
11
12
13
14
15
16
17
18
19
20
Features
10 VB + Signaling for standard UART (LSB-First,
9 VSP
Idle is 1)
8 CSA Baud rate 9600 or 19200 baud for the
communication:
7 VCC TP - UART <--> Host - Controller
6 DIV Direct coupling to host controller (TxD,
5 SAVE RxD), or via optical couplers (optional)
4 TSTIN 2 - wire protocol with software handshake
3 VIF Buffering of send frames
2 RESn
No critical timing during transmission
1 TxD
64 Byte telegram buffer
Operating temperature range:
-25°C to 85°C
Supervision of EIB bus voltage
GENERAL DESCRIPTION
The TP - UART - IC (Twisted Pair - Universal Asynchronous Receive Transmit - IC) is a
transceiver which supports the connection of microcontrollers of sensors, actuators, or other
applications to the EIB (European - Installation - Bus).
This module supports every transmit- and receive - function and also the high ohmic decoupling
of energy from bus line. It generates further a stabilized 3.3V or 5V supply to use by a host
controller. Up to 256 subscribers can be connected to one bus line.
An UART interface is realized for communication with a host controller. The coupling can be
realized directly or via optical couplers.
The TP - UART - IC consists of two main parts: the digital part (UART - Interface) and the analog
part ( analog circuit part).
The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All
rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes
reserved.
25.15.10.41.33a
25.10.01
page 1




EIB-TP-UART-IC pdf, 반도체, 판매, 대치품
TP-UART-IC
1.2 DC and AC Characteristics
The following parameters are valid in the ambient temperature range ϑamb = -25 οC to 85 οC
and for bus voltage VB+ = 20 to 33 V if it is not otherwise declared. When the bus voltage is
lower than 20 V and no RESET is active then the normal functionality must be fulfilled, but
the parameters may be outside the limits.
1.2.1 Bus Pins VB+ and VB- (Pins 10, 11)
Via these pins the ASIC is connected to the bus line. VB- represents the reference potential.
Symbol Parameter
Min Max Unit Note
VVB+ positive line voltage
-0.5 45 V 1)
Inormal current consumption in analog mode (without clock)
1 mA
Inormal current consumption in normal mode (with clock)
1.6 mA 4,9152 MHz
1) during surge impulse is allowed and guaranteed by ext. Elements: -20 V for 2 µs and 65 V for 150 µs
1.2.2 Buffer Voltage VSP (Pin 9)
The ASIC delivers a supply voltage of 5 volts to external loads. In order to prevent a rapid
change of bus current as a result of a rapid change of the load an external capacitor at the
pin VSP is used for energy storage. The static voltage is adjusted to app. 8,8 V (8,2 ...9,2)
by an internal regulator.
Symbol Parameter
Min Max Unit
VVSP Energy buffer voltage
5.76
13 V
CVSP External storage capacitor
80 µF
1) due to the limited current changing rate an overshoot of VVSP after load change may occur
2) recommended 100 µF; must be larger than the capacitor at VCC
Note
1)
2)
1.2.3 Current Controlling Pin CSA (Pin 8)
An external capacitor at this pin prevents a quick change of ASIC current in case of quick
changing bus voltage VB+ or load current IVCC. The ASIC current changes with a rate of
max. 0,5 mA/ms (CCSA = 47 nF).
Symbol Parameter
Min Max Unit Note
CCR max. current changing rate (ext. Start, CCSA = 47 nF) 0.2 0.5 mA/ms 1)
1)tolerance of capacitor CCSA = 47nF/50V +/- 5%
The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All
rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes
reserved.
25.15.10.41.33a
25.10.01
page 4

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EIB-TP-UART-IC 전자부품, 판매, 대치품
TP-UART-IC
1.2.11 Interface Pin TxD (Pin 1)
The UART interface output pin TxD transmits the information to host controller. The high
output level is derived from external voltage supply VIF. This pin is ESD protected to VB-
and VIF.
In normal mode: LOW pulse at EIB bus à TxD3 = HIGH à TxD = LOW
In analog mode: LOW pulse at EIB bus à TxD3 = HIGH à TxD = HIGH
Symbol
VOH
VOL
tr, tf
Parameter
output voltage high
output voltage low
rise time, fall time (10 %
90 %)
Min
VIF - 0.8
Max
0.5
100
Unit
V
V
ns
Note
IOH = -5 mA
IOL = 5 mA
CL = 150 pF
1.2.12 Reset Pin RESn (Pin 2)
This pin is an I / O pin with internal pull - up resistor to VIF.
In case of a reset the reset pin RESn delivers an active LOW signal to external host
controller. The output driver is realized as open drain (NMOS - transistor). The reset state
RESn = LOW can be caused by an internal RESET or by an external RESET due to forcing
an active LOW to the pin RESn. The switching levels are derived from external voltage
supply VIF. This pin is ESD protected to VB - and VIF.
Symbol Parameter
RPullUp value of internal pull-up resistor to VIF
VRESmax
VIL
VIH
Vhyst
VOL
VOL
VOL
maximum voltage at RES pin
voltage range for input low level
voltage range for input high level
hysteresis for switching level
output low voltage at 1V <= VCC < 4 V, IOL = 1 mA
output low voltage at VCC <= 1V, VIF > 3 V,
IOL = 1 mA
output low voltage at VCC >= 4 V, IOL = 3 mA
1) Switching level appr. VIF/2, i.e. VIF/2 ±Vhyst/2
Min
10
0
0.8 * VIF
0.1 * VIF
Max
25
VIF + 0.5
0.2 * VIF
1.0 * VIF
0.4 * VIF
0.2
0.2
0.4
Unit
k
V
V
V
V
Note
1)
1.2.13 Save PIN SAVE (Pin 5)
This pin is an NMOS open drain output with internal pullup resistor to VIF.
In case of break-down of the bus voltage for more than typ. 1.5 ms (save condition) this pin
delivers an active LOW signal to external host electronic. This pin is ESD protected to VB-
and VIF.
Symbol Parameter
Min
Max
Unit Note
RPullUp Value of internal pull-up resistor to VIF
10 25 k
Vmax maximum voltage at SAVE pin
VIF + 0.5 V
VOL Output LOW voltage at VCC >= 4V
0.4 V IOL = 3 mA
tFRG2 Delay from VB+ break-down to SAVE= LOW
0.7
3 ms Typ. 1.5 ms
In order to reach a Buffertime of at least 60 ms for VCC (IVCC 10 mA) the capacitor at VSP has to
be 470 µF ±20 %
The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All
rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes
reserved.
25.15.10.41.33a
25.10.01
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EIB-TP-UART-IC

TP-UART-IC

Siemens Semiconductor
Siemens Semiconductor

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