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PDF SLD-2000 Data sheet ( Hoja de datos )
| Número de pieza | SLD-2000 | |
| Descripción | 12 Watt Discrete LDMOS FET | |
| Fabricantes | Sirenza Microdevices | |
| Logotipo |  |
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Product Description
Sirenza Microdevices’ SLD2000 is a robust 12 Watt, high performance
LDMOS transistor die, designed for operation from 10 to 2700MHz. It
is an excellent solution for applications requiring high linearity and effi-
ciency. The SLD2000 is typically used as a driver or output stage for
power amplifier, or transmitter applications. These robust power tran-
sistors are fabricated using Sirenza’s high performance XEMOS IITM
process.
SLD-2000
12 Watt Discrete LDMOS FET -Bare Die
Functional Schematic Diagram
ESD
Protection
Product Features
• 12 Watt Output P1dB
• Single Polarity Operation
• 19dB Gain at 900 MHz
• XeMOS IITM LDMOS
• Integrated ESD Protection, Class 1B
• Aluminum Topside Metallization
• Gold Backside Metallization
Gate
Manifold
Drain
Manifold
Source - Backside Contact
Applications
• Base Station PA Driver
• Repeaters
• Military Communications
• RFID
• GSM, CDMA, Edge, WDCDMA
RF Specifications
Symbol
Parameter
Unit Min Typ Max
Frequency
Frequency of Operation
MHz
10
- 2700
Gain
10 Watt CW, 902 - 928MHz
dB - 19 -
Efficiency
Linearity
Drain Efficiency at 10 Watt CW, 915MHz
3rd Order IMD at 10 Watt PEP (Two Tone), 915MHz
% - 47 -
dBc - -32 -
Linearity
RTH
1dB Compression (P1dB)
Thermal Resistance (Junction-to-Case, mounted in package)
W - 12 -
ºC/W
-
4
-
Test Conditions: Mounted in ceramic package and tested in SirenzTa Evaluation Board VDS = 28.0V, IDQ = 150mA, TMounting Surface = 25ºC
DC Specifications
Symbol
gm
VGS Threshold
VDS Breakdown
Ciss
Crss
Coss
RDSON
Parameter
Forward Transconductance @ 125mA IDQ, VDS=28V
IDS=3mA
1mA VDS current
Input Capacitance (Gate to Source) VGS=0V, VDS=28V
Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V
Output Capacitance (Drain to Source) VGS=0V, VDS=28V
Drain to Source Resistance, VGS=10V VDS=250mV
Unit Min Typical Max
mA / V
590
V 3.0 3.8 5.0
V 65 70
pF 27.5
pF 0.8
pF 14.7
R 0.6 0.75
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such
information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
1 EDS-104292 Rev C
1 page  
Die Map
SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die
Dimensions Inches [mm]
0.0850 [2.16]
GATE
0.0450 [1.14]
SOURCE - BACKSIDE CONTACT - NOT SHOWN
DIE THICKNESS - 0.004 [0.10]
DRAIN
AuSi, AuSn, or AuGe eutectic die attach is recommended. AlSi bond wires are recommended.
303 S. Technology Court
Broomfield, CO 80021
Part Number Ordering Information
Part Number
Gel Pack
SLD-2000
100 pcs. per pack
Die are screened prior to dicing to DC parameters and
are shipped per Sirenza application note AN-039
Visual Criteria of Unpackaged Die.
Phone: (800) SMI-MMIC
5
http://www.sirenza.com
EDS-104292 Rev C
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet SLD-2000.PDF ] | |
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