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AD8175 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD8175은 전자 산업 및 응용 분야에서
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부품번호 AD8175 기능
기능 Video Crosspoint Switch
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AD8175 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
High channel count, triple 16 × 9 high speed, non-blocking
switch array
Differential or single-ended operation
Supports sync-on common-mode and sync-on color
operating modes
Decoded HV sync outputs available
G = +2 operation (differential input to differential output)
Flexible power supplies: +5 V or ±2.5 V
Logic ground for convenient control interface
Serial or parallel programming of switch array
High impedance output disable allows connection of
multiple devices with minimal loading on output bus
Adjustable output CM and black level through external pins
Excellent ac performance (to support 1600 × 1200 @ 85 Hz)
Bandwidth: 500 MHz
Slew rate: 1800 V/µs
Settling time: 4 ns to 1%
Low power of 3.5 W
Low all-hostile crosstalk
−88 dB @ 5 MHz
−46 dB @ 500 MHz
Wide input common-mode range of 4 V
Reset pin allows disabling of all outputs
Fully populated 26 x 26 ball PBGA package
(27 mm x 27 mm, 1 mm ball pitch)
Convenient grouping of RGB signals for easy routing
APPLICATIONS
RGB video switching
KVM
Professional video
GENERAL DESCRIPTION
The AD8175 is a high speed, triple 16 × 9 video crosspoint
switch matrix. It supports 1600 × 1200 RGB displays @ 85 Hz
refresh rate, by offering a 500 MHz bandwidth and a slew rate
of 1800 V/µs. With −88 dB of crosstalk and −94 dB isolation
(@ 5 MHz), the AD8175 is useful in many high speed video
applications.
The AD8175 supports two modes of operation: differential-in
to differential-out mode with sync-on CM signaling passed
through the switch and differential-in to differential-out mode
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
500 MHz, Triple 16 × 9
Video Crosspoint Switch
AD8175
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 VPOS VNEG VDD DGND
AD8175
SERIN
SER/PAR
WE
CLK
CS
UPDATE
RST
CMENC
45-BIT SHIFT
1 REGISTER WITH
5-BIT PARALLEL
0 LOADING
45
PARALLEL LATCH
45
A0
A1
A2
A3
SEROUT
DECODE
9 × 5:16 DECODERS
9
INPUT
RECEIVER
G = +1
2
R
2
G
2
B
144 OUTPUT
BUFFER
G = +1
2
2
2
SWITCH
MATRIX
G = +2
R
G
B
H
V
2
R
G2
B2
2
R
2G
2B
H
V
VBLK
VOCM_CMENCON
Figure 1.
VOCM_CMENCOFF
with CM signaling removed through the switch. The output
CM and black level can be conveniently set via external pins.
The independent output buffers of the AD8175 can be placed
into a high impedance state to create larger arrays by paralleling
crosspoint outputs. Inputs can be paralleled as well. The
AD8175 offers both serial and parallel programming modes.
The AD8175 is packaged in a fully-populated 26 × 26 ball
PBGA package and is available over the extended industrial
temperature range of −40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.




AD8175 pdf, 반도체, 판매, 대치품
Data Sheet
AD8175
SPECIFICATIONS
VS = ±2.5 V at TA = 25°C, G = +2, RL = 100 Ω (each output), VBLK = 0 V, output CM voltage = 0 V, differential I/O mode, unless
otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Flatness
Propagation Delay
Settling Time
Slew Rate, Differential Output
Slew Rate, RGB Common Mode
Slew Rate, HV Outputs
NOISE/DISTORTION PERFORMANCE
Crosstalk, All Hostile
Off Isolation, Input-Output
Input Voltage Noise
DC PERFORMANCE
Gain Error
Gain Matching
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Offset Voltage
Output Offset Voltage,
RGB Common Mode
Output Impedance
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
Output Current
INPUT CHARACTERISTICS
Input Voltage Range,
Differential Mode
Input Voltage Range,
Common Mode
CMR, RGB Input
CM Gain, RGB Input
Input Capacitance
Input Resistance
Input Offset Current
Conditions
200 mV p-p
2 V p-p
0.1 dB, 200 mV p-p
2 V p-p
1% , 2 V step
2 V step
2 V step, 10% to 90%
1 V step, 10% to 90%
Rail-to-rail, TTL load
ƒ = 5 MHz
ƒ = 10 MHz
ƒ = 100 MHz
ƒ = 500 MHz
ƒ = 5 MHz, RL = 100 Ω, one channel
0.01 MHz to 100 MHz
Min
R, G, B same channel
CMENC on or off
Temperature coefficient
CMENC on or off
Temperature coefficient
Enabled, differential
Disabled, differential
Disabled
Disabled
No load, differential
Short circuit
1
VIN = 1 V p-p, differential
ΔVOUT, DM/ΔVIN, CM, ΔVIN, CM = ±0.5 V, CMENC off
ΔVOUT, DM/ΔVIN, CM, ΔVIN, CM = ±0.5 V, CMENC on
ΔVOUT, CM/ΔVIN, CM, ΔVIN, CM = ±0.5 V CMENC off
ΔVOUT, CM/ΔVIN, CM, ΔVIN, CM = ±0.5 V, CMENC on
Any switch configuration
Differential
Typ
500
450
25
1.3
4
1800
1500
300
400
−88
−82
−58
−46
−94
40
1
0.5
40
10
31
10
−7.6
1.5
2.7
2
1
45
1.2
±2.25
–62
−45
−70
0
2
3.33
1
Max
4
Unit
MHz
MHz
MHz
ns
ns
V/µs
V/µs
V/µs
V/µs
dB
dB
dB
dB
dB
nV/√Hz
%
%
ppm/°C
mV
µV/°C
mV
µV/°C
kΩ
pF
µA
V p-p
mA
V p-p
V
dB
dB
dB
dB
pF
kΩ
µA
Rev. B | Page 3 of 40

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AD8175 전자부품, 판매, 대치품
AD8175
Data Sheet
TIMING CHARACTERISTICS (PARALLEL MODE)
Specifications subject to change without notice.
Table 7.
Parameter
Parallel Data Setup Time
WE Pulse Width
Parallel Hold Time
WE Pulse Separation
WE to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On
RST Time
Symbol
t1
t2
t3
t4
t5
t6
Limit
Min Typ Max Unit
80 ns
110 ns
150 ns
90 ns
10 ns
90 ns
80 ns
140 200 ns
1
WE
0
1
D0 TO D4
A0 TO A4
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t2
t1 t3
Table 8. Logic Levels, VDD = 3.3 V
VIH VIL VOH
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3, UPDATE
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3, UPDATE
SEROUT
2.0 V min
0.6 V max
Disabled
t4
t5 t6
Figure 3. Timing Diagram, Parallel Mode
VOL
SEROUT
Disabled
IIH
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3, UPDATE
20 µA max
IIL
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3, UPDATE
−20 µA max
IOH
SEROUT
Disabled
IOL
SEROUT
Disabled
Table 9. H and V Logic Levels, VDD = 3.3 V
VOH
VOL
2.7 V min
0.5 V max
IOH
–3 mA max
IOL
3 mA max
Table 10. RST Logic Levels, VDD = 3.3 V
VIH VIL
2.0 V min
0.6 V max
IIH
−60 µA max
IIL
−120 µA max
Table 11. CS Logic Levels, VDD = 3.3 V
VOH
VOL
2.0 V min
0.6 V max
IIH
100 µA max
IOL
40 µA max
Rev. B | Page 6 of 40

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