PDF AM29LV002B Data sheet ( Hoja de datos )

Número de pieza	AM29LV002B
Descripción	CMOS 3.0 Volt-only Boot Sector Flash Memory
Fabricantes	AMD
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No Preview Available ! Am29LV002B Data Sheet The Am29LV002B is not offered for new designs. Please contact a Spansion representative for alter- nates. The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 21520 Revision D Amendment 5 Issue Date October 11, 2006 1 page DATA SHEET TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10 Table 1. Am29LV002B Device Bus Operations .............................. 10 Requirements for Reading Array Data ................................... 10 Writing Commands/Command Sequences ............................ 10 Program and Erase Operation Status .................................... 11 Standby Mode ........................................................................ 11 Automatic Sleep Mode ........................................................... 11 RESET#: Hardware Reset Pin ............................................... 11 Output Disable Mode .............................................................. 11 Table 2. Am29LV002BT Top Boot Block Sector Address Table..... 12 Table 3. Am29LV002BB Bottom Boot Block Sector Address Table 12 Autoselect Mode ..................................................................... 12 Table 4. Am29LV002B Autoselect Codes (High Voltage Method).. 12 Sector Protection/Unprotection ............................................... 13 Temporary Sector Unprotect .................................................. 13 Hardware Data Protection ...................................................... 13 Figure 1. Temporary Sector Unprotect Operation ...........................13 Low VCC Write Inhibit .............................................................. 13 Write Pulse “Glitch” Protection ............................................... 13 Logical Inhibit .......................................................................... 13 Power-Up Write Inhibit ............................................................ 13 Figure 2. In-System Sector Protect/Unprotect Algorithms ...............14 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15 Reading Array Data ................................................................ 15 Reset Command ..................................................................... 15 Autoselect Command Sequence ............................................ 15 Byte Program Command Sequence ....................................... 15 Unlock Bypass Command Sequence ..................................... 16 Chip Erase Command Sequence ........................................... 16 Figure 3. Program Operation ..........................................................16 Sector Erase Command Sequence ........................................ 17 Erase Suspend/Erase Resume Commands ........................... 17 Figure 4. Erase Operation ...............................................................18 Command Definitions ............................................................. 19 Table 5. Am29LV002B Command Definitions................................. 19 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 20 DQ7: Data# Polling ................................................................. 20 Figure 5. Data# Polling Algorithm ...................................................20 RY/BY#: Ready/Busy# ........................................................... 21 DQ6: Toggle Bit I .................................................................... 21 DQ2: Toggle Bit II ................................................................... 21 Reading Toggle Bits DQ6/DQ2 ............................................... 21 Figure 6. Toggle Bit Algorithm ........................................................ 22 DQ5: Exceeded Timing Limits ................................................ 22 DQ3: Sector Erase Timer ....................................................... 22 Table 6. Write Operation Status..................................................... 23 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24 Figure 7. Maximum Negative Overshoot Waveform ...................... 24 Figure 8. Maximum Positive Overshoot Waveform ........................ 24 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .............................................................................. 26 Figure 10. Typical ICC1 vs. Frequency ........................................... 26 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11. Test Setup ..................................................................... 27 Table 7. Test Specifications ........................................................... 27 Figure 12. Input Waveforms and Measurement Levels ................. 27 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Operations .................................................................... 28 Figure 13. Read Operations Timings ............................................. 28 Hardware Reset (RESET#) .................................................... 29 Figure 14. RESET# Timings .......................................................... 29 Erase/Program Operations ..................................................... 30 Figure 15. Program Operation Timings .......................................... 31 Figure 16. Chip/Sector Erase Operation Timings .......................... 32 Figure 17. Data# Polling Timings (During Embedded Algorithms) . 33 Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 33 Figure 19. DQ2 vs. DQ6 ................................................................. 34 Temporary Sector Unprotect .................................................. 34 Figure 20. Temporary Sector Unprotect Timing Diagram .............. 34 Figure 21. Sector Protect/Unprotect Timing Diagram .................... 35 Alternate CE# Controlled Erase/Program Operations ............ 36 Figure 22. Alternate CE# Controlled Write Operation Timings ...... 37 Erase and Programming Performance . . . . . . . 38 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39 TS 040—40-Pin Standard TSOP* .......................................... 39 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision A (January 1998) ..................................................... 40 Revision B (June 1998) .......................................................... 40 Revision B+1 (August 1998) ................................................... 40 Revision C (January 1999) ..................................................... 40 Revision D (November 18, 1999) ........................................... 40 Revision D+1 (November 13, 2000) ....................................... 40 Revision D+2 (June 14, 2004) ................................................ 40 Revision D+3 (January 5, 2006) ............................................. 40 Revision D+4 (September 12, 2006) ...................................... 40 21520D5 October 11, 2006 Am29LV002B 3 5 Page DATA SHEET array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteris- tics” for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ± 0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.3 V, the standby current will be greater. If RESET# is asserted during a program or erase oper- ation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo- rithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high imped- ance state. 21520D5 October 11, 2006 Am29LV002B 9 11 Page

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