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EM636165-XXI 데이터시트 PDF




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부품번호 EM636165-XXI 기능
기능 1Mega x 16 Synchronous DRAM
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EM636165-XXI 데이터시트, 핀배열, 회로
EtronTech
EM636165-XXI
1Mega x 16 Synchronous DRAM (SDRAM)
Preliminary (Rev. 1.1, 04/2005)
Features
Fast access time: 5/5.5/6.5/7.5 ns
Fast clock rate: 166/143/125/100 MHz
Self refresh mode: standard and low power
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V±0.3V power supply
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
Lead Free Package available
Key Specifications
tCK3
tRAS
tAC3
tRC
EM636165
Clock Cycle time(min.)
Row Active time(max.)
Access time from CLK(max.)
Row Cycle time(min.)
-6I/7I/8I/10I
6/7/8/10ns
36/42/48/60 ns
5/5.5/6.5/7.5 ns
54/63/72/90 ns
Pin Assignment (Top View)
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE#
CAS#
RAS#
CS#
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 Vss
49 DQ15
48 DQ14
47 VSSQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38 VDDQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 Vss
Ordering Information
Industrial Operating temperature: -40~85°C
Part Number
Frequency
EM636165TS-6I/6IG
166MHz
EM636165TS-7I/7IG
143MHz
EM636165TS-8I/8IG
125MHz
EM636165TS-10I/10IG
100MHz
G : indicates Lead Free Package
Package
TSOP II
TSOP II
TSOP II
TSOP II
Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured
as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command
which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a
programmable mode register, the system can choose the most suitable modes to maximize its performance. These
Etron Technology, Inc.
No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.




EM636165-XXI pdf, 반도체, 판매, 대치품
EtronTech
1M x 16 SDRAM EM636165-XXI
LDQM,
UDQM
Input
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent
I/O buffer controls. The I/O buffers are placed in a high-z state when
LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is
sampled HIGH during a write cycle. Output data is masked (two-clock latency)
when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15-
DQ8, and LDQM masks DQ7-DQ0.
DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
NC - No Connect: These pins should be left unconnected.
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V± 0.3V )
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
(0V)
VDD Supply Power Supply: +3.3V ± 0.3V
VSS Supply Ground
Preliminary
4 Rev. 1.1 Apr. 2005

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EM636165-XXI 전자부품, 판매, 대치품
EtronTech
1M x 16 SDRAM EM636165-XXI
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto
precharge function may be interrupted by a subsequent Read or Write command to the same bank
or the other active bank before the end of the burst length. It may be interrupted by a
BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read
command can occur on any clock cycle following a previous Read command (refer to the following
figure).
T0 T1
T2 T3
T4 T5
T6 T7
T8
CLK
C OM M A ND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O
contention, a single cycle with high-impedance on the DQ pins must occur between the last read
data and the Write command (refer to the following three figures). If the data output of the burst
read occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at
least one clock prior to the Write command to avoid internal bus contention.
CLK
DQM
T0 T1
T2 T3
T4 T5
T6 T7
T8
C OM M A ND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
DQ's
: "H" or "L"
DOUT A0
Must be Hi-Z before
the Write Command
DINB0
DINB1
Read to Write Interval (Burst Length 4, CAS# Latency = 3)
NOP
DINB2
Preliminary
7 Rev. 1.1 Apr. 2005

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EM636165-XXI

1Mega x 16 Synchronous DRAM

Etron Technology
Etron Technology

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