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EM638325 데이터시트 PDF




Etron Technology에서 제조한 전자 부품 EM638325은 전자 산업 및 응용 분야에서
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부품번호 EM638325 기능
기능 2M x 32 Synchronous DRAM
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EM638325 데이터시트, 핀배열, 회로
EtronTech
EM638325
2M x 32 Synchronous DRAM (SDRAM)
Preliminary (Rev 1.4 October/2005)
Features
Clock rate: 200/183/166/143/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
Four internal banks (512K x 32bit x 4bank)
Programmable Mode
- CAS# Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
Burst stop function
Individual byte controlled by DQM0-3
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
Single +3.3V ± 0.3V power supply
Interface: LVTTL
Package: 400 x 875 mil, 86 Pin TSOP II, 0.50mm
pin pitch
Lead Free Package available
Ordering Information
Part Number
Leaded / Lead Free Package
EM638325TS-5/-5G
EM638325TS-5.5/-5.5G
EM638325TS-6/-6G
EM638325TS-7/-7G
EM638325TS-8/-8G
EM638325TS-10/-10G
Frequency
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
Package
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II
Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86 VSS
8 5 DQ15
84 VSSQ
8 3 DQ14
8 2 DQ13
8 1 VDDQ
8 0 DQ12
7 9 DQ11
78 VSSQ
7 7 DQ10
7 6 DQ9
7 5 VDDQ
7 4 DQ8
7 3 NC
72 VSS
71 DQM1
7 0 NC
6 9 NC
6 8 CLK
6 7 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
5 7 NC
5 6 DQ31
5 5 VDDQ
5 4 DQ30
5 3 DQ29
52 VSSQ
5 1 DQ28
5 0 DQ27
4 9 VDDQ
4 8 DQ26
4 7 DQ25
46 VSSQ
4 5 DQ24
44 VSS
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.




EM638325 pdf, 반도체, 판매, 대치품
EtronTech
2Mega x 32 SDRAM EM638325
NC - No Connect: These pins should be left unconnected.
VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VDD Supply Power Supply: +3.3V±0.3V
VSS Supply Ground
Preliminary
4
Rev 1.4
Oct. 2005

4페이지










EM638325 전자부품, 판매, 대치품
EtronTech
T0 T 1
T2
2Mega x 32 SDRAM
T3 T4 T5 T6
EM638325
T7 T8
CL K
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DOUT A0 DOUT A1
DOUT A2 DOUT A3
DOUT A0 DOUT A1
DOUT A2 DOUT A3
Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3)
NOP
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write command to the same bank or the other active
bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).
T0 T 1
T2 T3
T4 T5
T6 T7
T8
CLK
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DOUT A0 DOUT B0
DOUT B1 DOUT B2
DOUT B3
DOUT A0 DOUT B0
DOUT B1 DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following three figures). If the data output of the burst read occurs at the
second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
Preliminary
7
Rev 1.4
Oct. 2005

7페이지


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부품번호상세설명 및 기능제조사
EM638325

2M x 32 Synchronous DRAM

Etron Technology
Etron Technology

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