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PDF EM6622 Data sheet ( Hoja de datos )
| Número de pieza | EM6622 | |
| Descripción | Ultra-low power microcontroller | |
| Fabricantes | EM Microelectronic | |
| Logotipo |  |
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EM MICROELECTRONIC - MARIN SA
EM6622
Ultra Low Power Microcontroller with 4x32 LCD Driver
Features
• Low Power - 3.0 µA active mode, LCD On
- 0.6 µA standby mode, LCD Off
- 0.2 µA sleep mode
@ 1.5 V, 32 KHz, 25 ºC
• Low Voltage - 1.2 to 3.6 V
• 2 clocks per instruction cycle
• 72 basic instructions
• ROM 4k x 16 bits
• RAM 128 x 4 bits
• Max. 12 inputs ; port A, port B, port SP
• Max. 8 outputs ; port B, port SP
• Voltage Level Detector, 8 levels software
selectable from 1.2 V up to 4.0 V
• Melody, 7 tones + silence inclusive 4-bit timer
• Universal 10-bit counter, PWM, event counter
• Prescaler down to 1 second ( crystal = 32 KHz )
• 1/1000 sec 12 bit binary coded decimal counter
with hard or software start/stop function
• LCD 32 Segments, 3 or 4 times multiplexed
• 3 wire serial port , 8 bit, master and slave mode
• 5 external interrupts (port A, serial interface)
• 8 internal interrupts (3x prescaler, BCD counter
2x10-bit counter, melody timer, serial interface)
• timer watchdog and oscillation supervisor
Description
The EM6622 is an advanced single chip low cost
CMOS 4-bit microcontroller. It contains ROM, RAM,
LCD driver, power on reset, watchdog timer,
oscillation detection circuit, 10-bit up/down and
event counter, 1ms BCD counter, prescaler, voltage
level detector (Vld), serial interface and several
clock functions. The low voltage feature and low
power consumption make it the most suitable
controller for battery, stand alone and mobile
equipment. The EM6622 is manufactured using EM
Microelectronic's advanced low power (ALP) CMOS
process.
Typical Applications
• Timing device
• Automotive controls with display
• Intelligent display driver
• Measurement equipment
• Domestic appliance
• Interactive system with display
• Timer / sports timing devices
• Bicycle computers
• Safety and security devices
Figure 1. Architecture
Figure 2. Pin Configuration, TQFP64 10 * 10 * 1 mm
Copyright 2002, EM Microelectronic-Marin SA
1
03/02 REV. C/445
www.emmicroelectronic.com
1 page  
EM6622
Chip TQFP DIL
64 64 Signal Name
Function
Remarks
46 51
43
PSP[0]
Input/output , open drain
Serial interface data in
serial port : SIN
or
parallel out terminal 0
parallel data[0] in/out
47 52
44
PSP[1]
Output , open drain
Serial interface Ready CS
serial port : Ready/CS
or
parallel out terminal 1
parallel data[1] in/out
48 53
45
PSP[2]
Output , open drain
Serial interface data out
serial port : SOUT
or
parallel out terminal 2
parallel data[2] in/out
49 54
46
PSP[3]
Input/output , open drain
Serial interface clock I/O
serial port : SCLK
or
parallel out terminal 3
parallel data[3] in/out
50 55
47
PB[0]
Input/output, open drain
Port B data[0] I/O or
port B terminal 0
Ck[1] output
51 56
48
PB[1]
Input/output, open drain
Port B data[1] I/O or
port B terminal 1
Ck[11] output
52 57
49
PB[2]
Input/output, open drain
Port B data[2] I/O or
port B terminal 2
Ck[16] output
53 58
50
PB[3]
Input/output, open drain
Port B data[3] I/O or
port B terminal 3
PWM output
54 59
51
PA[0]
Input port A terminal 0
TestVar 1 ; Event counter
55 60
52
PA[1]
Input port A terminal 1
TestVar 2
56 61
53
PA[2]
Input port A terminal 2
TestVar 3
57 62
54
PA[3]
Input port A terminal 3
Event counter, MSC start/stop
58 63
55
Buzzer
Output Buzzer terminal
59 64
56
Strobe
Output Strobe terminal
µP reset state or/and port B write
or sleep flag out
60 1
57 Vbat = VDD
Positive power supply
MFP Connection
61 2
58
Vreg
Internal voltage regulator
Connect to minimum 100nF,
MFP connection
62 3
59 Qin/Osc1
Crystal terminal 1
32 KHz crystal, MFP connection
63 4
60 Qout /Osc2
Crystal terminal 2
32 KHz crystal, MFP connection
64 5
61
VSS
Negative power supply
ref. terminal, MFP connection
Gray shaded areas : Terminals needed for MFP programming connections (VDD, Vreg, Qin, Qout, Test).
Figure 3. Typical Configuration
L C D D is p la y
C rysta l
A ll C a p a c ito rs 1 0 0 n F
C1
VL1
C O M [4 :1 ]
S E G [3 2 :1 ]
Q in O out
C1 VL2
C1
VL3
Reset
C2
C1A
C1B
C2 C2A
C2B
EM 6622
V D D (V bat)
V reg
Port A
Test
Port B
Port S P
Buzzer
S tro b e
VSS
C3 C4
Copyright 2002, EM Microelectronic-Marin SA
5
03/02 REV. C/445
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5 Page 
EM6622
4.4 Digital Watchdog Timer Reset
The digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will
generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by
activating an inhibit digital watchdog bit (NoLogicWD) located in RegVldCntl. At power up, and after any
system reset, the watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system reset
signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the
watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a
system reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and
timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer
operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode
for more than 2.5 seconds.
From a system reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog
timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. It
is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every
second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the
counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’ {WDVal1 WDVal0}. When going into
the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the system reset
which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always reads ‘0’.
Table 4.4.1 Watchdog Timer Register RegSysCntl2
Bit Name
Reset
R/W
Description
3
WDReset
0
R/W Reset the Watchdog
1 -> Resets the Logic Watchdog
0 -> No action
The Read value is always '0'
2
SleepEn
0
R/W See Operating modes (sleep)
1
WDVal1
0
R Watchdog timer data Ck[1] divided by 4
0
WDVal0
0
R Watchdog timer data Ck[1] divided by 2
4.5 CPU State after Reset
Reset initializes the CPU as shown in Table 4.5.1 below.
Table 4.5.1 Initial CPU Value after Reset.
Name
Bits
Program counter 0
12
Program counter 1
12
Program counter 2
12
Stack pointer
2
Index register
7
Carry flag
1
Zero flag
1
Halt 1
Instruction register
16
Symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
Periphery registers 4 Reg.
Copyright 2002, EM Microelectronic-Marin SA
11
Initial Value
hex 000 (as a result of Jump 0)
Undefined
Undefined
PSP[0] selected
Undefined
Undefined
Undefined
0
Jump 0
See peripheral memory map
03/02 REV. C/445
www.emmicroelectronic.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM6622.PDF ] | |
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