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PDF EM6640 Data sheet ( Hoja de datos )

Número de pieza EM6640
Descripción Low Power Microcontroller
Fabricantes EM Microelectronic 
Logotipo EM Microelectronic Logotipo



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No Preview Available ! EM6640 Hoja de datos, Descripción, Manual

EM MICROELECTRONIC - MARIN SA
EM6640
Low Power Microcontroller
with EEPROM AND RC Oscillator
Features
Low Power - 42µA active mode
- 8µA standby mode
- 0.3µA sleep mode
@ 3.0V, 600kHz, 25°C, typ
Voltage Range - 1.9 to 5.5 V
Supply voltage level detection (SVLD)
ROM
- 1280 × 16 bit
RAM
- 80 × 4 bit
EEPROM - 32 x 8 bit
2 clocks per instruction cycle
72 basic instructions
RC oscillator
Oscillation detection circuit / Digital watchdog
timer reset.
Maximum 12 inputs (3 ports)
Maximum 8 outputs (2 ports)
Serial Write Buffer - 256 bits (SWB)
10 bit up/down counter with PWM capability
Frequency out 600kHz, 37.5kHz, 2.3kHz, PWM
Sleep Counter Reset (SCR) programmable.
8 internal interrupt sources (3×prescaler,
2×timer ,1xSWB, 1×SVLD, 1xEEPROM)
4 external interrupt sources (port A)
Reset with input combinations
Packages available : TSSOP16, SO16, SO18
Description
The EM6640 is an advanced single chip CMOS 4-bit
microcontroller. It contains ROM, RAM, EEPROM,
watchdog timer, oscillation detection circuit, 10 bit
up/down counter, prescaler, supply voltage level
detector (SVLD), sleep counter reset (SCR),
frequency output and SWB.
The low voltage feature and low power consumption
make it the most suitable controller for battery, stand
alone and mobile equipment. The EM66XX series is
manufactured using EM Microelectronic’s Advanced
Low Power (ALP) CMOS Process.
Typical Applications
remote controls
medical applications
domestic appliance
safety and security devices
measurement equipment
interactive system
keyless entry with rolling code
Figure 1 Architecture
Figure 2 Pin Configuration of TSSOP16
Copyright 2002, EM Microelectronic-Marin SA
1
03/02 REV. C/446
www.emmicroelectronic.com

1 page




EM6640 pdf
EM6640
2.1 ACTIVE Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Go into standby mode via the halt instruction or go into sleep mode by writing the sleep bit.
2.2 STANDBY Mode
Figure 4 Mode transition diagram
Executing a HALT instruction puts the EM6640 into
STANDBY mode. The voltage regulator, oscillator,
watchdog timer, interrupts and timers/counters are
operating. However, the CPU stops since the clock
ACTIVE
related to instruction execution stops. Registers,
HALT
RAM and I/O pins retain their states prior to
Instruction
STANDBY mode. STANDBY is canceled by a
RESET or an Interrupt request if enabled.
IRQ
SLEEP bit
write
2.3 SLEEP Mode
Writing the Sleep bit in the RegSysCntl1 register
puts the EM6640 in SLEEP mode. The oscillator
stops and most functions of the EM6640 are
inactive. To be able to write the Sleep bit, the
SleepEn bit in RegSysCntl2 must first be set to "1".
In SLEEP mode only the voltage regulator is active.
The RAM data integrity is maintained. SLEEP mode
may be canceled only by the Input Reset from PortA
or the Sleep Counter Reset.
STANDBY
RESET=1
RESET=0
SLEEP
RESET=1
RESET
RESET=1
During SLEEP mode and the following start up the EM6640 is in reset state. Waking up from SLEEP mode clears
the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to determine if the EM6640 was powered
up (SleepEn = "0") or woken up from SLEEP mode (SleepEn = "1").
The bit NoInputRes in option register OptPaRst is inhibited is sleep mode.
TAKE CARE !!! To quit SLEEP mode, one must be sure to have a suitable defined combination of PortA inputs
for reset (see section 4.3).
Table 2.3.1 shows the state of the EM6640 functions in STANDBY and SLEEP modes
FUNCTION
Oscillator
Oscillator Watchdog
Instruction Execution
Interrupt Functions
Registers and Flags
EEPROM
RAM data
Option Registers
Timer/Counter's
Logic Watchdog
Input PortA
I/O Port B
I/O Port C
SCR
SWB
Voltage Level Detector
STANDBY
Active
Active
Stopped
Active
Retained
Retained
Retained
Retained
Active
Active
Active
NoInputRes = "0"
Active
Active
Stopped
Active
finishes on going measure, then stop
SLEEP
Stopped
Stopped
Stopped
Stopped
Reset
Retained
Retained
Retained
Reset
Reset
Active
NoInputRes = "x"
High Impedance, no pulls
High Impedance, no pulls
Active if enable
Stopped
Stopped
3. Power Supply
The EM6640 is supplied by a single external power supply between VDD (VBat) and VSS (GND). A built-in
voltage regulator generates VregLogic providing regulated voltage for the oscillator and the internal logic. An
external capacitor (CVreg) has to be put on Vreg terminal (see Standard Operating Conditions, on page 55).
Vreg terminal is not intended to be used with external load except CVreg.
Copyright 2002, EM Microelectronic-Marin SA
5
03/02 REV. C/446
www.emmicroelectronic.com

5 Page





EM6640 arduino
EM6640
4.5 Digital Watchdog Timer Reset
The Digital Watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of CK[1]. It will
generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by activating
an inhibit digital watchdog bit (NoLogicWD) located in RegSysCtl3. By metal 1 mask option, one can force the
Digital Watchdog to be always active, this mean that the bit NoLogicWD has no more effect (see: Digital
Watchdog Option, page 50). In that case, the read of the bit NoLogicWD will always give ‘0’. By default, the
Digital Watchdog can be controlled by the register RegSysCtl3. At power up, and after any System Reset, the
watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the System Reset
signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the
watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 600kHz), or a
System Reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and timer
operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer operates
also in the STANDBY mode and thus, to avoid a System Reset, STANDBY should not be active for more than 2.5
seconds.
From a System Reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog
timer is reset at any other time, then it could become active after just 2.5 seconds. In addition, using the
Prescaler reset function can lower this minimum watchdog time. It is therefore recommended to use the Prescaler
IRQ1Hz interrupt to periodically reset the watchdog every one second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the counting
sequence is (on each rising edge of CK[1]) : {WDVal1 WDVal0} ‘00’, ‘01’, ‘10’, ‘11’. When in the ‘11’ state, the
watchdog reset will be active within ½ second. The watchdog reset activates the system reset which in turn
resets the watchdog. If the watchdog is inhibited its timer is reset and therefore always reads ‘0’.
Table 4.5.1 Watchdog timer register RegSysCntl2
Bit Name
Reset
R/W
3
WDReset
0
R/W
2
SleepEn
0
R/W
1
WDVal1
0
R
0
WDVal0
0
R
Description
Reset the Watchdog
1 -> Resets the Logic Watchdog
0 -> no action
The Read value is always '0'
see Operating modes (sleep)
Watchdog timer data 1/4 ck[1]
Watchdog timer data 1/2 ck[1]
Copyright 2002, EM Microelectronic-Marin SA
11
03/02 REV. C/446
www.emmicroelectronic.com

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