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기능 Ultra Low Power 8-pin Microcontroller
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EM6680 데이터시트, 핀배열, 회로
R EM MICROELECTRONIC - MARIN SA
EM6680
Ultra Low Power 8-pin Microcontroller
Features
‰ True Low Power:
4.0 µA active mode
3.0 µA standby mode
0.65 µA sleep mode
@ 1.5V, 32kHz, 25°C
‰ Low Supply Voltage 1.2 V to 3.6 V
‰ No external component needed
‰ Available in TSSOP-8/14, SO-8/14 packages and die
‰ 4-bit ADC or 12 levels Supply Voltage Level
Detector (SVLD)
‰ Max 4 (5*) outputs with 2 high drive outputs of 10mA
‰ Max. 5 (6*) inputs
‰ Sleep Counter Reset (automatic wake-up from sleep
mode (EM patent))
‰ Mask ROM 1536 × 16 bits
‰ RAM 80 × 4 bits
‰ Internal RC oscillator 32 kHz – 800 kHz
‰ 2 clocks per instruction cycle
‰ 72 basic instructions
‰ External CPU clock source possible
‰ Watchdog timer (2 sec)
‰ Power-On-Reset with Power-Check on Start-Up
‰ 3 wire serial port , 8 bit, master and slave mode
‰ Universal 10-bit counter, PWM, event counter
‰ Prescaler down to 1 Hz (freq. = 32 kHz)
‰ Frequency output 1Hz, 2048 Hz, CpuClk, PWM
‰ 6 internal interrupt sources ( 2×10-bit counter, 2×
prescaler, SVLD, Serial Interface)
‰ 2 external interrupt sources (port A)
Description
The EM6680 is an ultra-low voltage, low power
microcontroller coming in a package as small as 8-pin
TSSOP and working up to 0.4 MIPS. It comes with an
integrated 4-bit ADC and 2 high current drive outputs of
10mA and it requires no external component. It has a
sleep counter reset allowing automatic wake-up from sleep
mode. It is designed for use in battery-operated and field-
powered applications requiring an extended lifetime. A
high integration level make it an ideal choice for cost
sensitive applications.
The EM6680 contains the equivalent of 3kB mask ROM
and a RC oscillator with frequencies between 32 and
800kHz selectable by metal option. It also has a power-
on reset, watchdog timer, 10 bit up/down counter, PWM
and several clock functions.
Tools include windows-based simulator and emulator. A
ROMless version is also available for validation in
development stage (EMDK6680A).
Figure 1. Architecture
Stable
RC oscillator
32 - 128kHz
Prescaler
10-Bit Univ
Count/Timer
Interrupt
Controller
ROM
1536 x 16Bit
RAM
80 x 4Bit
Core
EM6600
VDD
VDD
Power Supply
Power on
Reset
Sleep Counter
Reset
Watchdog
4-bit ADC
SVLD check
Port A
Serial Interface
PA0 PA1 PA2
PA3
Reset
PA4 *PA5
PA1 & PA2:
high current
drive outputs
* PA5 available only
in 14-pin package
and in die
Figure 2. Pin Configuration
TSSOP-8, SO-8
PA0 1
PA1 2
PA2 3
PA3 4
8 VDD
EM6680 7 VREG
6 PA4 (Reset,ADC)
5 VSS
TSSOP-14, SO-14
NC 1
14 NC
PA0 2
13 VDD
PA1 3
12 VREG
PA2 4 EM6680 11 PA5
PA3 5
10 PA4 (Reset,ADC)
NC 6
9 VSS
NC 7
8 NC
Typical Applications
‰ Household appliances
‰ Safety and security devices
‰ Automotive controls
‰ Sensor interfaces
‰ Watchdog
‰ Intelligent ADC
‰ Driver (LED, triac)
Copyright © 2005, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com




EM6680 pdf, 반도체, 판매, 대치품
R
EM6680
1. Pin Description for EM6680
Table 1 EM6680 pin descriptions
# On
Chip
SO-8
Signal
Name
Description
1 1 PA0 general I/O, serial In, Wake-Up on Change, IRQ source,…
2 2 PA1 general I/O, serial CLK, timer source, external clock
3 3 PA2 general I/O, serial Out, freq., CPU reset status output,…
4 4 PA3 general I/O, serial Rdy/Cs, Interrupt source, Reset
5 5 Vss ground – negative supply pin
6 6 PA4 general I, Reset, timer source, Interrupt source, Wake-Up, Compare I
7* NC PA5 general I/O, freq, Wake-Up on Change, IRQ source
8 7 Vreg regulated voltage supported by 100nF tw. Vss
9 8 Vdd positive supply pin – capacitance tw. Vdd (C depends on Vdd noise)
Figure 3. Typical configuration for Vdd > 1.5V
Vdd
Vdd
Vbat C
I/O pad
Voltage
regulator
SVLD
4-bit ADC
Level Shifter
uPUS 4bits core
Digital peripherals
RAM 64 x 4 bits
ROM 1536 x 16 bits
Analog peripherals
RC oscillator
Power-on-Reset
Sleep Reset Cnt
Vreg
Vreg
Capacitor
100nF
C
Vss
For Vdd > 1.5V
Figure 4. Typical configuration for Vdd < 1.5V
Vdd
Vdd
Vbat C
I/O pad
Voltage
regulator
SVLD
4-bit ADC
Level Shifter
Regulated Voltage
uPUS 4bits core
Digital peripherals
RAM 64 x 4 bits
ROM 1536 x 16 bits
Analog peripherals
RC oscillator
Power-on-Reset
Sleep Reset Cnt
Typ_config_vdd+15.vsd
Vreg
Vreg
Capacitor
100nF
C
Vss
For Vdd > 1.5V
Typ_config_vdd+15.vsd
NOTE: State of I/O pads may not be defined until Vreg reaches typ. 0.8V and Power-On-Reset logic
supplied by Vreg clears them to Inputs.
On I/O pins there are protective diodes towards Vdd and Vss.
Copyright © 2005, EM Microelectronic-Marin SA
4
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EM6680 전자부품, 판매, 대치품
R
EM6680
4. Reset
Figure 6. illustrates the reset structure of the EM6680. One can see that there are five possible reset sources :
(1) Internal initial Power On Reset (POR) circuitry with Power-Check.Æ POR, ResetCold, System Reset, Reset CPU
(2) External reset from PA[3/4] if software enabled
Æ System Reset, Reset CPU
(3) Internal reset from the Digital Watchdog.
Æ System Reset, Reset CPU
(4) Internal reset from the Sleep Counter Reset.
Æ System Reset, Reset CPU
(5) Wake-Up on change from PA[0/5] or PA[3/4] if software enabled. Æ System Reset, Reset CPU
Table 4.1 Reset sources that can be used in different Operating modes
Reset Sources
ACTIVE mode
STAND-BY mode
POR (static) with Power Check
Software enabled reset on PA[3/4]
Digital Watch-Dog Timer
Sleep Counter Reset
Wake Up on Change from Sleep
Going in Sleep mode
XS = software enable
Yes
XS dig. debounce
XS
No
No
Yes
Yes
XS dig. debounce
XS
No
No
No
SLEEP mode
Yes
XS analog debounce
No
XS
XS
No
Figure 6. EM6680 Reset Structure
RESETs generation logic diagram
Write- Reset
Read Statuts
Ck[1]
WDVal
WDVa
Watchdog
times
NoWDtim
SCRsel0
SCRsel1
Sleep Counter
Reset Oscillator
typ . 100Hz
Prescaler
Write- Active
Read Statuts
SleepEn
Sleep
Sleep
Analogue
Filter
resetCold
System Reset
Delay
ck[ 1 5]
ResSys
Peripherals
&
CPU
Wake up (on change)
Debounce
InResAH
ck[9]
PA[3]
PA[4]
PA[3/4]Resin
POR &
Power-check
Rd RegSysCntl1
Set
Reset
PORstatus
All signals enter bottom, left, top and output on the right side of the boxes
POR
All reset sources activate the System Reset (ResSys). The ‘System Reset Delay’ ensures that the system reset
remains active long enough for all system functions to be reset (active for 12 system clock cycles. CPU is reset
by the same reset
As well as activating the system reset, the POR also resets all bits in registers marked ‘p’ and the sleep enable
(SleepEn) latch. System reset does not reset these register bits, nor the sleep enable latch.
Copyright © 2005, EM Microelectronic-Marin SA
7
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