PDF EM6A9325 Data sheet ( Hoja de datos )

Número de pieza	EM6A9325
Descripción	4M x 32 Low Power SDRAM
Fabricantes	Etron Technology
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No Preview Available ! EtronTech EM6A9325 4M x 32 Low Power SDRAM (LPSDRAM) Preliminary (Rev 0.4 June/2003) Features • Clock rate: 133/125/100 MHz • Fully synchronous operation • Internal pipelined architecture • Four internal banks (1M x 32bit x 4bank) • Programmable Mode - CAS# Latency: 1, 2 & 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential & Interleave - Burst-Read-Single-Write • Burst stop function • Individual byte controlled by DQM0-3 • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • Single 2.5V power supply • Interface: LVCMOS •Package : 90 ball-FBGA, 11x13mm, Lead Free Ordering Information Part Number Frequency EM6A9325BG-7.5G() 133MHz EM6A9325BG-8G() 125MHz EM6A9325BG-1H/LG() 100MHz () : G indicates Lead free package Package 11x13 BGA 11x13 BGA 11x13 BGA Pin Assignment : Top View 12 A DQ26 B DQ28 C VSSQ D VSSQ E VDDQ F VSS G A4 H A7 J CLK K DQM1 L VDDQ M VSSQ N VSSQ P DQ11 R DQ13 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 4567 8 9 VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS# VDD DQ6 DQ1 VDDQ VDD DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS# WE# DQ7 DQ5 DQ3 VSSQ DQ0 DQ21 DQ19 VDDQ VDD1Q VSSQ VDD A1 A11 RAS# DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. 1 page EtronTech 4M x 32 LPSDRAM EM6A9325 Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command State CKEn-1 CKEn DQM(6) BS0,1 A10 A11, A9-0 CS# RAS# CAS# WE# BankActivate Idle(3) HXX V Row address L L H H BankPrecharge Any H X X V L X L L H L PrechargeAll Any H X X X H X L L H L W rite Active(3) H X X Write and AutoPrecharge Active(3) H X X V L Column L H L L address V H (A0 ~ A7) L H L L Read Active(3) H X X Read and Autoprecharge Active(3) H X X V L Column L H L H address V H (A0 ~ A7) L H L H Mode Register Set Idle H X X OP code LL L L No-Operation Any H X X X X X L H H H Burst Stop Active(4) H X X XX X LH H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle L H X X X X H X X X (SelfRefresh) LH H H Clock Suspend Mode Entry Active H L X XX X HX X X LH H H Power Down Mode Entry Any(5) HL X XX X HX X X LH H H Clock Suspend Mode Exit Active LHX XX X XX X X Power Down Mode Exit Any L H X X X X H X X X (PowerDown) LH H H Data Write/Output Enable Active H X L X X X X X X X Data Mask/Output Disable Active H X H XX X XX X Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 6. DQM0-3 X Preliminary 5 Rev 0.4 June 2003 5 Page EtronTech 4M x 32 LPSDRAM EM6A9325 7 Write and AutoPrecharge command (refer to the following figure) (RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. 8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A11-A0 = Register Data) The mode register stores the data for controlling the various operating modes of SDRAM. The Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins BA0,1 and A11~A0 in the same cycle is the data written to the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. CLK CKE CS# RAS# CAS# WE# ADDR. DQM DQ Hi-Z T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 tCK2 Clock min. Address Key tRP PrechargeAll Mode Register Any Set Command Command Mode Register Set Cycle (CAS# Latency = 2, 3) Preliminary 11 Rev 0.4 June 2003 11 Page

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