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PDF ISL59482 Data sheet ( Hoja de datos )
| Número de pieza | ISL59482 | |
| Descripción | Multiplexing Amplifiers | |
| Fabricantes | Intersil Corporation | |
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Dual, 500MHz Triple, Multiplexing Amplifiers
ISL59482
The ISL59482 contains two independent fixed gain of 2 triple
4:1 MUX amplifiers that feature high slew rate and excellent
bandwidth for RGB video switching. Each RGB 4:1 MUX
contains binary coded, channel select logic inputs (S0, S1),
and separate logic inputs for High Impedance Output (HIZ) and
power-down (EN) modes. The HIZ state presents a high
impedance at the output so that both RGB MUX outputs can be
wired together to form an 8:1 RGB MUX amplifier or, they can
be used in R-R, G-G, and B-B pairs to form a 4:1 differential
input/output MUX. Separate power-down mode controls (EN1,
EN2,) are included to turn off unneeded circuitry in power
sensitive applications. With both EN pins pulled high, the
ISL59482 enters a standby power mode consuming just
34mW.
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59482
S1-1, 2 S0-1, 2 EN1, 2 HIZ1, 2
OUTPUT1, 2
00
00
IN0 (A, B, C)
01
00
IN1 (A, B, C)
10
00
IN2 (A, B, C)
11
00
IN3 (A, B, C)
X X 1 X Power-down
XX 0 1
High Z
Features
• Dual, triple 4:1 multiplexers for RGB
• 520MHz bandwidth into 500Ω load
• ±1600 V/µs slew rate
• Externally configurable for various video MUX circuits
including:
- 8:1 RGB MUX
- Two separate 4:1 RGB MUX
- 4:1 differential RGB video MUX
• Internally fixed gain-of-2
• High impedance outputs (HIZ)
• Power-down mode (EN)
• ±5V operation
• Supply current 16mA/Ch maximum
• Pb-free (RoHS compliant)
Applications
• HDTV/DTV analog inputs
• Video projectors, computer monitors
• Set-top boxes
• Security video
• Broadcast video equipment
S0-1
S1-1
DECODE1
HIZ1
EN1
S0-2
S1-2
DECODE2
HIZ2
EN2
EN0-1
EN1-1
EN2-1
EN3-1
IN0(A1, B1, C1)
IN1(A1, B1, C1)
IN2(A1, B1, C1)
IN3(A1, B1, C1)
AMPLIFIER1 BIAS
EN0-2
EN1-2
EN2-2
EN3-2
IN0(A2, B2, C2)
IN1(A2, B2, C2)
IN2(A2, B2, C2)
IN3(A2, B2, C2)
AMPLIFIER2 BIAS
+- OUT(A1, B1, C1)
OUT(A2, B2, C2)
+-
FIGURE 1. ISL59482 FUNCTIONAL DIAGRAM
August 8, 2014
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FN6209.4
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL59482
Electrical Specifications V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25°C, Input Video = 0.5VP-P and RL = 500Ω to GND,
CL = 5pF unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN MAX
(Note 7) TYP (Note 7) UNIT
BW Small Signal -3dB Bandwidth
Large Signal -3dB Bandwidth
FBW
0.1dB Bandwidth
SR Slew Rate
TRANSIENT RESPONSE
VOUT = 0.2VP-P; RL = 500Ω, CL = 1.2pF
VOUT = 0.2VP-P; RL = 150Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 500Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 150Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 500Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 150Ω, CL = 1.2pF
25% to 75%, RL = 150Ω, Input Enabled,
CL = 1.5pF
520
420
250
230
35
90
1600
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
tr, tf Large Signal Large Signal Rise, Fall Times, tr, tf,
10% to 90%
tr, tf, Small
Signal
Small Signal Rise, Fall Times, tr, tf,
10% to 90%
ts 0.1%
Settling Time to 0.1%
ts 1%
Settling Time to 1%
SWITCHING CHARACTERISTICS
VOUT = 2VP-P; RL = 500Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 150Ω, CL = 1.2pF
VOUT = 0.2VP-P; RL = 500Ω, CL = 1.2pF
VOUT = 0.2VP-P; RL = 150Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 500Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 150Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 500Ω, CL = 1.2pF
VOUT = 2VP-P; RL = 150Ω, CL = 1.2pF
1.2 ns
1.2 ns
0.7 ns
0.8 ns
22 ns
24 ns
5 ns
7 ns
VGLITCH
tSW-L-H
Channel-to-Channel Switching Glitch
EN Switching Glitch
HIZ Switching Glitch
Channel Switching Time Low-to-High
VIN = 0V, CL = 1.2pF
VIN = 0V, CL = 1.2pF
VIN = 0V, CL = 1.2pF
1.2V logic threshold to 10% movement of
analog output
60 mVP-P
200 mVP-P
300 mVP-P
22 ns
tSW-H-L
Channel Switching Time High-to-Low
1.2V logic threshold to 10% movement of
analog output
25
ns
tpd Propagation Delay
10% to 10%
0.9 ns
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Submit Document Feedback
5
FN6209.4
August 8, 2014
5 Page 
AC Test Circuits (Continued)
ISL59482
VIN
50Ω
or
75Ω
ISL59482
RS
CL 50Ω or 75Ω
5pF
TEST
EQUIPMENT
50Ω
or
75Ω
FIGURE 27C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE
DEGRADED.
FIGURE 27. TEST CIRCUITS
Figure 27A illustrates the optimum output load for testing AC
performance. Figure 27B illustrates the optimum output load
when connecting to a 50Ω input terminated equipment.
Application Information
General
The ISL59482 is ideal as the matrix element of high
performance switchers and routers. Key features include internal
fixed gain of 2, high impedance buffered analog inputs and
excellent AC performance at output loads down to 150Ω for
video cable-driving. The current feedback output amplifiers are
stable operating into capacitive loads.
Ground Connections
For the best isolation and crosstalk rejection, all GND pins must
connect to the GND plane.
Power-up Considerations
The ESD protection circuits use internal diodes from all pins the V+
and V- supplies. In addition, a dV/dT- triggered clamp is connected
between the V+ and V- pins, as shown in the Equivalent Circuits 1
through 4 section of the “Pin Description” on page 3. The dV/dT
triggered clamp imposes a maximum supply turn-on slew rate of
1V/µs. Damaging currents can flow for power supply rates-of-rise in
excess of 1V/µs, such as during hot plugging. Under these
conditions, additional methods should be employed to ensure the
rate of rise is not exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic input
pins. Schottky diodes (Motorola MBR0550T or equivalent)
connected from V+ to ground and V- to ground (Figure 28) will
shunt damaging currents away from the internal V+ and V- ESD
diodes in the event that the V+ supply is applied to the device
before the V- supply. One Schottky can be used to protect both V+
power supply pins, and a second for the protection of both V-
pins.
If positive voltages are applied to the logic or analog video input
pins before V+ is applied, current will flow through the internal
ESD diodes to the V+ pin. The presence of large decoupling
capacitors and the loading effect of other circuits connected to
V+, can result in damaging currents through the ESD diodes and
other active circuits within the device. Therefore, adequate
current limiting on the digital and analog inputs is needed to
prevent damage during the time the voltages on these inputs are
more positive than V+.
HIZ State
Each internal 4:1 triple MUX-amp has a three-state output control
pin (HIZ1 and HIZ2). Each has a an internal pull-down resistor to
set the output to the enabled state with no connection to the HIZ
pin. The HIZ state is established within approximately 20ns by
placing a logic high (>2V) on the HIZ pin. If the HIZ state is
selected, the output is a high impedance 1.4MΩ with
approximately 1.5pF in parallel with a 10µA bias current from
the output. When more than one MUX shares a common output,
the high impedance state loading effect is minimized over the
maximum output voltage swing and maintains its high Z even in
the presence of high slew rates. The supply current during this
state is the same as the active state.
EN and Power-down States
The EN pins are active low. An internal pull-down resistor ensures
the device will be active with no connection to the EN pins. The
Power-down state is established within approximately 80ns, if a
logic high (>2V) is placed on the EN pins. In the Power-down
state, supply current is reduced significantly by shutting the three
amplifiers off. The output presents a high impedance to the
output pin, however, there is a risk that the disabled amplifier
output can be back-driven at signal voltage levels exceeding
2VP-P. Under this condition, large incoming slew rates can cause
fault currents of tens of mA. Therefore, the parallel connection of
multiple outputs is not recommended unless the application can
tolerate the limited power-down output impedance.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than 50mA.
Adequate thermal heat sinking of the parts is also required.
Submit Document Feedback 11
FN6209.4
August 8, 2014
11 Page | ||
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| PDF Descargar | [ Datasheet ISL59482.PDF ] | |
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