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PDF ISL59534 Data sheet ( Hoja de datos )

Número de pieza ISL59534
Descripción 32x16 Video Crosspoint
Fabricantes Intersil Corporation 
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No Preview Available ! ISL59534 Hoja de datos, Descripción, Manual

®
Data Sheet
February 7, 2007
ISL59534
FN6249.5
32x16 Video Crosspoint
The ISL59534 is a 300MHz 32x16 Video Crosspoint Switch.
Each input has an integrated DC-restore clamp and an input
buffer. Each output has a fast On-Screen Display (OSD)
switch (for inserting graphics or other video) and an output
buffer. The switch is non-blocking, so any combination of
inputs to outputs can be chosen, including one channel
driving multiple outputs. The Broadcast Mode directs one
input to all 16 outputs. The output buffers can be individually
controlled through the SPI interface, the gain can be
programmed to +1 or +2, and each output can be placed into
a high impedance mode.
The ISL59534 offers a typical -3dB signal bandwidth of
300MHz. Differential gain of 0.025% and differential gain of
0.05°, along with 0.1dB flatness out to 50MHz, make the
ISL59534 suitable for many video applications.
The switch matrix configuration and output buffer gain are
programmed through an SPI/QSPI™-compatible three-wire
serial interface. The ISL59534 interface is designed to
facilitate both fast updates and initialization. On power-up, all
outputs are high impedance to avoid output conflicts.
Thewww.DataSheet4U.com ISL59534 is available in a 356 ball BGA package and
specified over an extended -40°C to +85°C temperature range.
The single-supply ISL59534 can accommodate input signals
from 0V to 3.5V and output voltages from 0V to 3.8V. Each
input includes a clamp circuit that restores the input level to
an externally applied reference in AC-coupled applications.
The ISL59535 is a fully differential input version of this device.
Features
• 32x16 non-blocking switch with buffered inputs and
outputs
• 300MHz typical bandwidth
• 0.025%/0.05° dG/dP
• Output gain switchable +1 or +2 for each channel
• Individual outputs can be put in a high impedance state
• -90dB Isolation at 6MHz
• SPI digital interface
• Single +5V supply operation
• Pb-free plus anneal available (RoHS compliant)
Applications
• Security camera switching
• RGB routing
• HDTV routing
Ordering Information
PART NUMBER TAPE &
(Note)
REEL
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL59534IKEZ
- 356 Ld BGA
V356.27x27A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
VREF
32 VIDEO
INPUTS
IN0 - IN31
CLAMP
VS VOVERn
OVERn
16 OVERLAY
VIDEO INPUTS
16 OVERLAY
CHANNEL
ENABLES
32x16
SWITCH
MATRIX
16 VIDEO
OUTPUTS
OUT0 – OUT15
SDI
SCLK
SLATCH
CLAMP
CLAMP
ENABLE
SPI INTERFACE AND
CONTROL REGISTERS
AV
X1, X2
OUTPUT
ENABLE
VSDO
SDO
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

1 page




ISL59534 pdf
ISL59534
Pin Descriptions (Continued)
NAME NUMBER
DESCRIPTION
VREF
M3 DC-restore clamp reference input. In an
AC-coupled configuration (DC-Restore
clamp enabled), the sync tip of
composite video inputs will be restored
to this level. Set to 0.3 to 0.7V for
optimum performance.
In an DC-coupled configuration
(DC-Restore clamp disabled), this pin
should be tied to ground.
Do not let the VREF pin float! A
floating VREF pin drifts high and, if the
clamp function is enabled, will cause all
of the outputs to simultaneously try to
drive ~4V DC into their 150Ω loads.
SLATCH
J3 Serial Latch. Serial data is latched into
ISL59534 on rising edge of SLATCH.
SCLK
K3 Serial data clock
SDI L3 Serial data input
SDO
G3 Serial data output. Can be tied to SDI of
another ISL59534 to enable
daisy-chaining of multiple devices.
RESET
H3 Reset input. Pull high then low to reset
device, but not needed in normal
operation. Tie to ground in final applica-
tion.
VSDO
D3 Power supply for SDO pin. Tie to +5V
for a 0 to 5V SDO output signal swing.
VS +5V power supply
GND
Ground
NC No Connect - Do not electrically con-
nect to anything, including ground.
5 FN6249.5
February 7, 2007

5 Page





ISL59534 arduino
Typical Performance Curves (Continued)
ISL59534
AV = 1
RL = 150Ω
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
FIGURE 31. DIFFERENTIAL GAIN, AV = 1
AV = 1
RL = 150Ω
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
FIGURE 32. DIFFERENTIAL PHASE, AV = 1
AV = 1
RL = 150Ω
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
FIGURE 33. DIFFERENTIAL GAIN, AV = 1
AV = 1
RL = 150Ω
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
FIGURE 34. DIFFERENTIAL GAIN, AV = 1
AV = 2
RL = 150Ω
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
FIGURE 35. DIFFERENTIAL GAIN, AV = 2
11
AV = 2
RL = 150Ω
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
FIGURE 36. DIFFERENTIAL PHASE, AV = 2
FN6249.5
February 7, 2007

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